[PATCH 3/16] Kconfig update for lemote fulong mini-PC

[PATCH 3/16] Kconfig update for lemote fulong mini-PC

[zhangfx]

[-- Attachment #1: Type: text/plain, Size: 1928 bytes --]


Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 arch/mips/Kconfig |   37 +++++++++++++++++++++++++++++++++++++
 1 files changed, 37 insertions(+), 0 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 338bfa3..cedb0fa 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -16,6 +16,26 @@ choice
 	prompt "System type"
 	default SGI_IP22
 
+config LEMOTE_FULONG
+	bool "Support for Lemote's fulong mini-PC"
+	select SYS_HAS_CPU_LOONGSON2
+	select DMA_NONCOHERENT
+	select BOOT_ELF32
+	select BOARD_SCACHE
+	select HW_HAS_PCI
+	select I8259
+	select ISA
+	select IRQ_CPU
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_64BIT_KERNEL
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_SUPPORTS_HIGHMEM
+	select SYS_HAS_EARLY_PRINTK
+	select GENERIC_HARDIRQS_NO__DO_IRQ
+	help
+        Lemote Fulong mini-PC board, which uses Chinese Loongson-2E CPU and a fpga north bridge 
+
+
 config MIPS_MTX1
 	bool "4G Systems MTX-1 board"
 	select DMA_NONCOHERENT
@@ -1142,6 +1162,13 @@ choice
 	prompt "CPU type"
 	default CPU_R4X00
 
+config CPU_LOONGSON2	
+	bool "LOONGSON2"
+	depends on SYS_HAS_CPU_LOONGSON2
+	select CPU_SUPPORTS_32BIT_KERNEL
+	select CPU_SUPPORTS_64BIT_KERNEL
+	select CPU_SUPPORTS_HIGHMEM
+
 config CPU_MIPS32_R1
 	bool "MIPS32 Release 1"
 	depends on SYS_HAS_CPU_MIPS32_R1
@@ -1352,6 +1379,9 @@ config CPU_SB1
 
 endchoice
 
+config SYS_HAS_CPU_LOONGSON2
+	bool
+
 config SYS_HAS_CPU_MIPS32_R1
 	bool
 
@@ -1681,6 +1711,13 @@ config CPU_HAS_SMARTMIPS
 config CPU_HAS_WB
 	bool
 
+config 64BIT_CONTEXT
+	bool "Save 64bit integer registers" if CPU_LOONGSON2 && 32BIT
+	help
+	  Loongson2 CPU is 64bit , when used in 32BIT mode, its integer registers
+	  can still be accessed as 64bit, mainly for multimedia instructions. We must have
+	  all 64bit save/restored to make sure those instructions to get correct result.
+
 #
 # Vectored interrupt mode is an R2 feature
 #
-- 
1.4.4.4

[PATCH 3/16] Kconfig update for lemote fulong mini-PC

[tiansm]

From: Fuxin Zhang <zhangfx@lemote.com>


Signed-off-by: Fuxin Zhang <zhangfx@lemote.com>
---
 arch/mips/Kconfig |   38 ++++++++++++++++++++++++++++++++++++++
 1 files changed, 38 insertions(+), 0 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 338bfa3..c18a835 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -16,6 +16,27 @@ choice
 	prompt "System type"
 	default SGI_IP22
 
+config LEMOTE_FULONG
+	bool "Support for Lemote's fulong mini-PC"
+	select SYS_HAS_CPU_LOONGSON2
+	select DMA_NONCOHERENT
+	select BOOT_ELF32
+	select BOARD_SCACHE
+	select HW_HAS_PCI
+	select I8259
+	select ISA
+	select IRQ_CPU
+	select SYS_SUPPORTS_32BIT_KERNEL
+	select SYS_SUPPORTS_64BIT_KERNEL
+	select SYS_SUPPORTS_LITTLE_ENDIAN
+	select SYS_SUPPORTS_HIGHMEM
+	select SYS_HAS_EARLY_PRINTK
+	select GENERIC_HARDIRQS_NO__DO_IRQ
+	select CPU_HAS_WB
+	help
+        Lemote Fulong mini-PC board, which uses Chinese Loongson-2E CPU and a fpga north bridge
+
+
 config MIPS_MTX1
 	bool "4G Systems MTX-1 board"
 	select DMA_NONCOHERENT
@@ -1142,6 +1163,13 @@ choice
 	prompt "CPU type"
 	default CPU_R4X00
 
+config CPU_LOONGSON2
+	bool "LOONGSON2"
+	depends on SYS_HAS_CPU_LOONGSON2
+	select CPU_SUPPORTS_32BIT_KERNEL
+	select CPU_SUPPORTS_64BIT_KERNEL
+	select CPU_SUPPORTS_HIGHMEM
+
 config CPU_MIPS32_R1
 	bool "MIPS32 Release 1"
 	depends on SYS_HAS_CPU_MIPS32_R1
@@ -1352,6 +1380,9 @@ config CPU_SB1
 
 endchoice
 
+config SYS_HAS_CPU_LOONGSON2
+	bool
+
 config SYS_HAS_CPU_MIPS32_R1
 	bool
 
@@ -1681,6 +1712,13 @@ config CPU_HAS_SMARTMIPS
 config CPU_HAS_WB
 	bool
 
+config 64BIT_CONTEXT
+	bool "Save 64bit integer registers" if CPU_LOONGSON2 && 32BIT
+	help
+	  Loongson2 CPU is 64bit , when used in 32BIT mode, its integer registers
+	  can still be accessed as 64bit, mainly for multimedia instructions. We must have
+	  all 64bit save/restored to make sure those instructions to get correct result.
+
 #
 # Vectored interrupt mode is an R2 feature
 #
-- 
1.4.4.1

Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Ralf Baechle]

On Sun, Apr 15, 2007 at 11:25:52PM +0800, tiansm@lemote.com wrote:

> @@ -1681,6 +1712,13 @@ config CPU_HAS_SMARTMIPS
>  config CPU_HAS_WB
>  	bool
>  
> +config 64BIT_CONTEXT
> +	bool "Save 64bit integer registers" if CPU_LOONGSON2 && 32BIT
> +	help
> +	  Loongson2 CPU is 64bit , when used in 32BIT mode, its integer registers
> +	  can still be accessed as 64bit, mainly for multimedia instructions. We must have
> +	  all 64bit save/restored to make sure those instructions to get correct result.
> +

Is there anything in implementation of this option Loongson2-specific?
If not then I suggest we make this option loook like:

   bool "Save 64bit integer registers" if CPU_SUPPORTS_64BIT_KERNEL && 32BIT

Somebody else might have a use for it!

  Ralf

Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Fuxin Zhang]

>> +
>>     
>
> Is there anything in implementation of this option Loongson2-specific?
>   
Yes. Most 64bit MIPS processors cannot access 64bit content of registers 
when it is in 32bit mode.

Loongson2 has no 32/64 mode bit in fact.

And the usage arise from Loongson2's multimedia extension, which is also 
uniq.
> If not then I suggest we make this option loook like:
>
>    bool "Save 64bit integer registers" if CPU_SUPPORTS_64BIT_KERNEL && 32BIT
>
> Somebody else might have a use for it!
>
>   Ralf
>
>
>
>
>   

RE: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Uhler, Mike]

> Yes. Most 64bit MIPS processors cannot access 64bit content 
> of registers when it is in 32bit mode.

For clarity, there is no 32/64-bit mode in MIPS processors.  There is a
mode in which 64-bit OPERATIONS are enabled (that is, those instructions
which operate on the full width of the registers) - See the definition
of 64-bit Operations Enable in the MIPS64 Architecture for Programmers,
volume III.  Note that such operations are always enabled while the
processor is running in Kernel Mode.

The patch is a little short on context, but if you've got a 64-bit
kernel, I had always assumed that save/restore of context is always done
with LD/SD, not by figuring out whether a process has 64-bit operations
enabled, then doing a conditional LD/SD or LW/SW.

/gmu
---
Michael Uhler, Chief Technology Officer
MIPS Technologies, Inc.   Email: uhler AT mips.com
1225 Charleston Road      Voice:  (650)567-5025   FAX:   (650)567-5225
Mountain View, CA 94043
   

> -----Original Message-----
> From: linux-mips-bounce@linux-mips.org 
> [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Fuxin Zhang
> Sent: Wednesday, April 18, 2007 6:32 AM
> To: Ralf Baechle
> Cc: tiansm@lemote.com; linux-mips@linux-mips.org; Fuxin Zhang
> Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC
> 
> 
> >> +
> >>     
> >
> > Is there anything in implementation of this option 
> Loongson2-specific?
> >   
> Yes. Most 64bit MIPS processors cannot access 64bit content 
> of registers when it is in 32bit mode.
> 
> Loongson2 has no 32/64 mode bit in fact.
> 
> And the usage arise from Loongson2's multimedia extension, 
> which is also uniq.
> > If not then I suggest we make this option loook like:
> >
> >    bool "Save 64bit integer registers" if 
> CPU_SUPPORTS_64BIT_KERNEL && 
> > 32BIT
> >
> > Somebody else might have a use for it!
> >
> >   Ralf
> >
> >
> >
> >
> >   
> 
> 

RE: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Uhler, Mike]

> Yes. Most 64bit MIPS processors cannot access 64bit content 
> of registers when it is in 32bit mode.

For clarity, there is no 32/64-bit mode in MIPS processors.  There is a
mode in which 64-bit OPERATIONS are enabled (that is, those instructions
which operate on the full width of the registers) - See the definition
of 64-bit Operations Enable in the MIPS64 Architecture for Programmers,
volume III.  Note that such operations are always enabled while the
processor is running in Kernel Mode.

The patch is a little short on context, but if you've got a 64-bit
kernel, I had always assumed that save/restore of context is always done
with LD/SD, not by figuring out whether a process has 64-bit operations
enabled, then doing a conditional LD/SD or LW/SW.

/gmu
---
Michael Uhler, Chief Technology Officer
MIPS Technologies, Inc.   Email: uhler AT mips.com
1225 Charleston Road      Voice:  (650)567-5025   FAX:   (650)567-5225
Mountain View, CA 94043
   

> -----Original Message-----
> From: linux-mips-bounce@linux-mips.org 
> [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Fuxin Zhang
> Sent: Wednesday, April 18, 2007 6:32 AM
> To: Ralf Baechle
> Cc: tiansm@lemote.com; linux-mips@linux-mips.org; Fuxin Zhang
> Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC
> 
> 
> >> +
> >>     
> >
> > Is there anything in implementation of this option 
> Loongson2-specific?
> >   
> Yes. Most 64bit MIPS processors cannot access 64bit content 
> of registers when it is in 32bit mode.
> 
> Loongson2 has no 32/64 mode bit in fact.
> 
> And the usage arise from Loongson2's multimedia extension, 
> which is also uniq.
> > If not then I suggest we make this option loook like:
> >
> >    bool "Save 64bit integer registers" if 
> CPU_SUPPORTS_64BIT_KERNEL && 
> > 32BIT
> >
> > Somebody else might have a use for it!
> >
> >   Ralf
> >
> >
> >
> >
> >   
> 
> 

Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Fuxin Zhang]

Uhler, Mike wrote:
>> Yes. Most 64bit MIPS processors cannot access 64bit content 
>> of registers when it is in 32bit mode.
>>     
>
> For clarity, there is no 32/64-bit mode in MIPS processors.  There is a
> mode in which 64-bit OPERATIONS are enabled (that is, those instructions
> which operate on the full width of the registers) - See the definition
> of 64-bit Operations Enable in the MIPS64 Architecture for Programmers,
> volume III.  Note that such operations are always enabled while the
> processor is running in Kernel Mode.
>
> The patch is a little short on context, but if you've got a 64-bit
> kernel, I had always assumed that save/restore of context is always done
> with LD/SD, not by figuring out whether a process has 64-bit operations
> enabled, then doing a conditional LD/SD or LW/SW.
>
>   
This patch for 32bit kernel. We want to save/restore 64bit register 
content because the high 32bit of register might be used by multimedia 
programs for loongson processor, such as mplayer.

> /gmu
> ---
> Michael Uhler, Chief Technology Officer
> MIPS Technologies, Inc.   Email: uhler AT mips.com
> 1225 Charleston Road      Voice:  (650)567-5025   FAX:   (650)567-5225
> Mountain View, CA 94043
>    
>
>   
>> -----Original Message-----
>> From: linux-mips-bounce@linux-mips.org 
>> [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Fuxin Zhang
>> Sent: Wednesday, April 18, 2007 6:32 AM
>> To: Ralf Baechle
>> Cc: tiansm@lemote.com; linux-mips@linux-mips.org; Fuxin Zhang
>> Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC
>>
>>
>>     
>>>> +
>>>>     
>>>>         
>>> Is there anything in implementation of this option 
>>>       
>> Loongson2-specific?
>>     
>>>   
>>>       
>> Yes. Most 64bit MIPS processors cannot access 64bit content 
>> of registers when it is in 32bit mode.
>>
>> Loongson2 has no 32/64 mode bit in fact.
>>
>> And the usage arise from Loongson2's multimedia extension, 
>> which is also uniq.
>>     
>>> If not then I suggest we make this option loook like:
>>>
>>>    bool "Save 64bit integer registers" if 
>>>       
>> CPU_SUPPORTS_64BIT_KERNEL && 
>>     
>>> 32BIT
>>>
>>> Somebody else might have a use for it!
>>>
>>>   Ralf
>>>
>>>
>>>
>>>
>>>   
>>>       
>>     
>
>
>
>
>   

Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Ralf Baechle]

On Wed, Apr 18, 2007 at 08:28:16AM -0700, Uhler, Mike wrote:

> > Yes. Most 64bit MIPS processors cannot access 64bit content 
> > of registers when it is in 32bit mode.
> 
> For clarity, there is no 32/64-bit mode in MIPS processors.  There is a
> mode in which 64-bit OPERATIONS are enabled (that is, those instructions
> which operate on the full width of the registers) - See the definition
> of 64-bit Operations Enable in the MIPS64 Architecture for Programmers,
> volume III.  Note that such operations are always enabled while the
> processor is running in Kernel Mode.
> 
> The patch is a little short on context, but if you've got a 64-bit
> kernel, I had always assumed that save/restore of context is always done
> with LD/SD, not by figuring out whether a process has 64-bit operations
> enabled, then doing a conditional LD/SD or LW/SW.

Here's a funny one where we have something like a mode.  This is a
reposting from Bill Earl:

[...]
     One other issue is that UX should always be set, to allow use of
MIPS3 instructions, and that XX (bit 31) should be set on R5000 and
R10000 processors, to enable MIPS4 instructions.  This in turn means
that, to avoid various illegal address exceptions, the VM system
should not allow a 32-bit user program to map anything into the top 32
KB of the user address space.

     The problem has to do with some compilers using integer
arithmetic to compute a base for some variables in the current stack
frame, and then using negative displacements to address the variables,
for cases where the stack frame exceeds 32 KB, but is located near the
top of memory.  The 32-bit unsigned integer add to, say, 0x7fffff00
(64-bit address 0x000000007fffff00) produces a signed 32-bit value
such as 0x80000f00, which is the 64-bit value 0xffffffff80000f00,
since all 32-bit values, signed or unsigned, are stored as 32-bit
signed values sign-extended to 64 bits.  When you do a load with a
negative offset of, say, -0x1000, you get an address
0xffffffff7fffff00, not 0x000000007fffff00.  With UX=0, this would be
fine, but, with UX=1 (to enable MIPS3 instructions), the above address
is illegal.  If the $sp is always at least 32 KB below the top of the
address space, this problem does not arise, since any such intermediate
pointer generated by the compiler will always be below 0x80000000.
[...]

The original posting is at http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=14452.59571.970106.514001%40liveoak.engr.sgi.com

  Ralf

RE: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Uhler, Mike]

Note that both of these apply to pre-MIPS64 processors.  In a MIPS64
implementation, The Status.PX bit should be used to enable 64-bit
operations without enabling 64-bit addressing.  The Status.XX bit is
gone and can't be set.  The addressing boundary condition that Bill
mentioned is explicitly address in the Architecture for Programmer's
manual, Volume III, section 4.10 as a requirement for hardware in
exactly this case.

I realize that Loongson is a MIPS III processor where Bill's suggestion
may apply, but it's not a general problem moving forward to MIPS64.

/gmu
---
Michael Uhler, Chief Technology Officer
MIPS Technologies, Inc.   Email: uhler AT mips.com
1225 Charleston Road      Voice:  (650)567-5025   FAX:   (650)567-5225
Mountain View, CA 94043
   

> -----Original Message-----
> From: Ralf Baechle [mailto:ralf@linux-mips.org] 
> Sent: Wednesday, April 18, 2007 9:38 AM
> To: Uhler, Mike
> Cc: Fuxin Zhang; tiansm@lemote.com; 
> linux-mips@linux-mips.org; Fuxin Zhang
> Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC
> 
> On Wed, Apr 18, 2007 at 08:28:16AM -0700, Uhler, Mike wrote:
> 
> > > Yes. Most 64bit MIPS processors cannot access 64bit content of 
> > > registers when it is in 32bit mode.
> > 
> > For clarity, there is no 32/64-bit mode in MIPS processors. 
>  There is 
> > a mode in which 64-bit OPERATIONS are enabled (that is, those 
> > instructions which operate on the full width of the 
> registers) - See 
> > the definition of 64-bit Operations Enable in the MIPS64 
> Architecture 
> > for Programmers, volume III.  Note that such operations are always 
> > enabled while the processor is running in Kernel Mode.
> > 
> > The patch is a little short on context, but if you've got a 64-bit 
> > kernel, I had always assumed that save/restore of context is always 
> > done with LD/SD, not by figuring out whether a process has 64-bit 
> > operations enabled, then doing a conditional LD/SD or LW/SW.
> 
> Here's a funny one where we have something like a mode.  This 
> is a reposting from Bill Earl:
> 
> [...]
>      One other issue is that UX should always be set, to allow use of
> MIPS3 instructions, and that XX (bit 31) should be set on 
> R5000 and R10000 processors, to enable MIPS4 instructions.  
> This in turn means that, to avoid various illegal address 
> exceptions, the VM system should not allow a 32-bit user 
> program to map anything into the top 32 KB of the user address space.
> 
>      The problem has to do with some compilers using integer 
> arithmetic to compute a base for some variables in the 
> current stack frame, and then using negative displacements to 
> address the variables, for cases where the stack frame 
> exceeds 32 KB, but is located near the top of memory.  The 
> 32-bit unsigned integer add to, say, 0x7fffff00 (64-bit 
> address 0x000000007fffff00) produces a signed 32-bit value 
> such as 0x80000f00, which is the 64-bit value 
> 0xffffffff80000f00, since all 32-bit values, signed or 
> unsigned, are stored as 32-bit signed values sign-extended to 
> 64 bits.  When you do a load with a negative offset of, say, 
> -0x1000, you get an address 0xffffffff7fffff00, not 
> 0x000000007fffff00.  With UX=0, this would be fine, but, with 
> UX=1 (to enable MIPS3 instructions), the above address is 
> illegal.  If the $sp is always at least 32 KB below the top 
> of the address space, this problem does not arise, since any 
> such intermediate pointer generated by the compiler will 
> always be below 0x80000000.
> [...]
> 
> The original posting is at 
> http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=1445
2.59571.970106.514001%40liveoak.engr.sgi.com
> 
>   Ralf
> 

RE: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Uhler, Mike]

Note that both of these apply to pre-MIPS64 processors.  In a MIPS64
implementation, The Status.PX bit should be used to enable 64-bit
operations without enabling 64-bit addressing.  The Status.XX bit is
gone and can't be set.  The addressing boundary condition that Bill
mentioned is explicitly address in the Architecture for Programmer's
manual, Volume III, section 4.10 as a requirement for hardware in
exactly this case.

I realize that Loongson is a MIPS III processor where Bill's suggestion
may apply, but it's not a general problem moving forward to MIPS64.

/gmu
---
Michael Uhler, Chief Technology Officer
MIPS Technologies, Inc.   Email: uhler AT mips.com
1225 Charleston Road      Voice:  (650)567-5025   FAX:   (650)567-5225
Mountain View, CA 94043
   

> -----Original Message-----
> From: Ralf Baechle [mailto:ralf@linux-mips.org] 
> Sent: Wednesday, April 18, 2007 9:38 AM
> To: Uhler, Mike
> Cc: Fuxin Zhang; tiansm@lemote.com; 
> linux-mips@linux-mips.org; Fuxin Zhang
> Subject: Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC
> 
> On Wed, Apr 18, 2007 at 08:28:16AM -0700, Uhler, Mike wrote:
> 
> > > Yes. Most 64bit MIPS processors cannot access 64bit content of 
> > > registers when it is in 32bit mode.
> > 
> > For clarity, there is no 32/64-bit mode in MIPS processors. 
>  There is 
> > a mode in which 64-bit OPERATIONS are enabled (that is, those 
> > instructions which operate on the full width of the 
> registers) - See 
> > the definition of 64-bit Operations Enable in the MIPS64 
> Architecture 
> > for Programmers, volume III.  Note that such operations are always 
> > enabled while the processor is running in Kernel Mode.
> > 
> > The patch is a little short on context, but if you've got a 64-bit 
> > kernel, I had always assumed that save/restore of context is always 
> > done with LD/SD, not by figuring out whether a process has 64-bit 
> > operations enabled, then doing a conditional LD/SD or LW/SW.
> 
> Here's a funny one where we have something like a mode.  This 
> is a reposting from Bill Earl:
> 
> [...]
>      One other issue is that UX should always be set, to allow use of
> MIPS3 instructions, and that XX (bit 31) should be set on 
> R5000 and R10000 processors, to enable MIPS4 instructions.  
> This in turn means that, to avoid various illegal address 
> exceptions, the VM system should not allow a 32-bit user 
> program to map anything into the top 32 KB of the user address space.
> 
>      The problem has to do with some compilers using integer 
> arithmetic to compute a base for some variables in the 
> current stack frame, and then using negative displacements to 
> address the variables, for cases where the stack frame 
> exceeds 32 KB, but is located near the top of memory.  The 
> 32-bit unsigned integer add to, say, 0x7fffff00 (64-bit 
> address 0x000000007fffff00) produces a signed 32-bit value 
> such as 0x80000f00, which is the 64-bit value 
> 0xffffffff80000f00, since all 32-bit values, signed or 
> unsigned, are stored as 32-bit signed values sign-extended to 
> 64 bits.  When you do a load with a negative offset of, say, 
> -0x1000, you get an address 0xffffffff7fffff00, not 
> 0x000000007fffff00.  With UX=0, this would be fine, but, with 
> UX=1 (to enable MIPS3 instructions), the above address is 
> illegal.  If the $sp is always at least 32 KB below the top 
> of the address space, this problem does not arise, since any 
> such intermediate pointer generated by the compiler will 
> always be below 0x80000000.
> [...]
> 
> The original posting is at 
> http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=1445
2.59571.970106.514001%40liveoak.engr.sgi.com
> 
>   Ralf
> 

Re: [PATCH 3/16] Kconfig update for lemote fulong mini-PC

[Ralf Baechle]

On Wed, Apr 18, 2007 at 03:27:16PM -0700, Uhler, Mike wrote:

> Note that both of these apply to pre-MIPS64 processors.  In a MIPS64
> implementation, The Status.PX bit should be used to enable 64-bit
> operations without enabling 64-bit addressing.  The Status.XX bit is
> gone and can't be set.  The addressing boundary condition that Bill
> mentioned is explicitly address in the Architecture for Programmer's
> manual, Volume III, section 4.10 as a requirement for hardware in
> exactly this case.
> 
> I realize that Loongson is a MIPS III processor where Bill's suggestion
> may apply, but it's not a general problem moving forward to MIPS64.

Linux limits the address space to 0x7fff8000 for 32-bit processes.  For
sake of simplicity and symmetry we do this on both 32-bit and 64-bit
kernels, on all processors.  A 64-bit kernel always runs userspace
processes with UX=1.  Since a 32-bit process cannot create mappings
above the low 2GB there isn't an actual need to use PX.

(I think there is a small bug in this scheme though, a process that is
accessing a 64-bit userspace address that isn't a 32-bit address should
be sent a SIGBUS but will actually receive a SIGSEGV.  But that's a
subtility and also requires extrapolating from an API documents that only
covers a strict 32-bit universe.)

  Ralf