From: John Crispin <blogic@openwrt.org>
To: Florian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, jogo@openwrt.org,
mbizon@freebox.fr, cernekee@gmail.com, dgcbueu@gmail.com
Subject: Re: [PATCH 3/3] MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value
Date: Sat, 11 Jan 2014 11:45:28 +0100 [thread overview]
Message-ID: <52D120C8.8020102@openwrt.org> (raw)
In-Reply-To: <1389386114-31834-4-git-send-email-florian@openwrt.org>
On 10/01/14 21:35, Florian Fainelli wrote:
> Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
> value of 4) instead of the currently configured 32 bytes L1-cache line
> size.
>
> Reported-by: Daniel Gonzalez<dgcbueu@gmail.com>
> Signed-off-by: Florian Fainelli<florian@openwrt.org>
> ---
> arch/mips/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 123f7c0..a3fec87 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -139,6 +139,7 @@ config BCM63XX
> select SWAP_IO_SPACE
> select ARCH_REQUIRE_GPIOLIB
> select HAVE_CLK
> + select MIPS_L1_CACHE_SHIFT_4
> help
> Support for BCM63XX based boards
>
Hi Florian,
why is this not part of 1/3
John
next prev parent reply other threads:[~2014-01-11 10:47 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-01-10 20:35 [PATCH 0/3] MIPS: L1_CACHE_SHIFT updates Florian Fainelli
2014-01-10 20:35 ` Florian Fainelli
2014-01-10 20:35 ` [PATCH 1/3] MIPS: introduce MIPS_L1_CACHE_SHIFT_<N> Florian Fainelli
2014-01-10 20:35 ` Florian Fainelli
2014-01-11 10:44 ` Jonas Gorski
2014-01-10 20:35 ` [PATCH 2/3] MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N> Florian Fainelli
2014-01-10 20:35 ` Florian Fainelli
2014-01-11 10:47 ` Jonas Gorski
2014-01-10 20:35 ` [PATCH 3/3] MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value Florian Fainelli
2014-01-10 20:35 ` Florian Fainelli
2014-01-11 10:45 ` John Crispin [this message]
2014-01-11 10:54 ` Jonas Gorski
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