[PATCH 0/3] MIPS: L1_CACHE_SHIFT updates

[PATCH 0/3] MIPS: L1_CACHE_SHIFT updates

[Florian Fainelli]

Ralf, John,

This patchset cleanups the MIPS_L1_CACHE_SHIFT values and also fixes it
for Broadcom BCM63xx DSL SOCs.

Thanks!

Florian Fainelli (3):
  MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>
  MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N>
  MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value

 arch/mips/Kconfig              | 27 +++++++++++++++++++++++----
 arch/mips/pmcs-msp71xx/Kconfig |  1 +
 arch/mips/ralink/Kconfig       |  1 +
 3 files changed, 25 insertions(+), 4 deletions(-)

-- 
1.8.3.2

[PATCH 0/3] MIPS: L1_CACHE_SHIFT updates

[Florian Fainelli]

Ralf, John,

This patchset cleanups the MIPS_L1_CACHE_SHIFT values and also fixes it
for Broadcom BCM63xx DSL SOCs.

Thanks!

Florian Fainelli (3):
  MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>
  MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N>
  MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value

 arch/mips/Kconfig              | 27 +++++++++++++++++++++++----
 arch/mips/pmcs-msp71xx/Kconfig |  1 +
 arch/mips/ralink/Kconfig       |  1 +
 3 files changed, 25 insertions(+), 4 deletions(-)

-- 
1.8.3.2

[PATCH 1/3] MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>

[Florian Fainelli]

In order to avoid keeping an ever growing list of chips which need to
select a specific MIPS_L1_CACHE_SHIFT value introduce multiple internal
and non-exposed Kconfig symbols for the various MIPS_L1_CACHE_SHIFT
values out there and update the relevant Kconfig symbols to select them.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
 arch/mips/Kconfig              | 18 ++++++++++++++++++
 arch/mips/pmcs-msp71xx/Kconfig |  1 +
 arch/mips/ralink/Kconfig       |  1 +
 3 files changed, 20 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 17cc7ff..753c5a3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -183,6 +183,7 @@ config MACH_DECSTATION
 	select SYS_SUPPORTS_128HZ
 	select SYS_SUPPORTS_256HZ
 	select SYS_SUPPORTS_1024HZ
+	select MIPS_L1_CACHE_SHIFT_4
 	help
 	  This enables support for DEC's MIPS based workstations.  For details
 	  see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
@@ -468,6 +469,7 @@ config SGI_IP22
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
+	select MIPS_L1_CACHE_SHIFT_7
 	help
 	  This are the SGI Indy, Challenge S and Indigo2, as well as certain
 	  OEM variants like the Tandem CMN B006S. To compile a Linux kernel
@@ -488,6 +490,7 @@ config SGI_IP27
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_NUMA
 	select SYS_SUPPORTS_SMP
+	select MIPS_L1_CACHE_SHIFT_7
 	help
 	  This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
 	  workstations.  To compile a Linux kernel that runs on these, say Y
@@ -694,6 +697,7 @@ config MIKROTIK_RB532
 	select SWAP_IO_SPACE
 	select BOOT_RAW
 	select ARCH_REQUIRE_GPIOLIB
+	select MIPS_L1_CACHE_SHIFT_4
 	help
 	  Support the Mikrotik(tm) RouterBoard 532 series,
 	  based on the IDT RC32434 SoC.
@@ -1088,6 +1092,18 @@ config FW_SNIPROM
 config BOOT_ELF32
 	bool
 
+config MIPS_L1_CACHE_SHIFT_4
+	bool
+
+config MIPS_L1_CACHE_SHIFT_5
+	def_bool y
+
+config MIPS_L1_CACHE_SHIFT_6
+	bool
+
+config MIPS_L1_CACHE_SHIFT_7
+	bool
+
 config MIPS_L1_CACHE_SHIFT
 	int
 	default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
@@ -1372,6 +1388,7 @@ config CPU_CAVIUM_OCTEON
 	select LIBFDT
 	select USE_OF
 	select USB_EHCI_BIG_ENDIAN_MMIO
+	select MIPS_L1_CACHE_SHIFT_7
 	help
 	  The Cavium Octeon processor is a highly integrated chip containing
 	  many ethernet hardware widgets for networking tasks. The processor
@@ -1794,6 +1811,7 @@ config IP22_CPU_SCACHE
 config MIPS_CPU_SCACHE
 	bool
 	select BOARD_SCACHE
+	select MIPS_L1_CACHE_SHIFT_6
 
 config R5000_CPU_SCACHE
 	bool
diff --git a/arch/mips/pmcs-msp71xx/Kconfig b/arch/mips/pmcs-msp71xx/Kconfig
index 3482b8c..6073ca4 100644
--- a/arch/mips/pmcs-msp71xx/Kconfig
+++ b/arch/mips/pmcs-msp71xx/Kconfig
@@ -6,6 +6,7 @@ config PMC_MSP4200_EVAL
 	bool "PMC-Sierra MSP4200 Eval Board"
 	select IRQ_MSP_SLP
 	select HW_HAS_PCI
+	select MIPS_L1_CACHE_SHIFT_4
 
 config PMC_MSP4200_GW
 	bool "PMC-Sierra MSP4200 VoIP Gateway"
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 424f034..1bfd1c1 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -15,6 +15,7 @@ choice
 
 	config SOC_RT288X
 		bool "RT288x"
+		select MIPS_L1_CACHE_SHIFT_4
 
 	config SOC_RT305X
 		bool "RT305x"
-- 
1.8.3.2

[PATCH 1/3] MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>

[Florian Fainelli]

In order to avoid keeping an ever growing list of chips which need to
select a specific MIPS_L1_CACHE_SHIFT value introduce multiple internal
and non-exposed Kconfig symbols for the various MIPS_L1_CACHE_SHIFT
values out there and update the relevant Kconfig symbols to select them.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
 arch/mips/Kconfig              | 18 ++++++++++++++++++
 arch/mips/pmcs-msp71xx/Kconfig |  1 +
 arch/mips/ralink/Kconfig       |  1 +
 3 files changed, 20 insertions(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 17cc7ff..753c5a3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -183,6 +183,7 @@ config MACH_DECSTATION
 	select SYS_SUPPORTS_128HZ
 	select SYS_SUPPORTS_256HZ
 	select SYS_SUPPORTS_1024HZ
+	select MIPS_L1_CACHE_SHIFT_4
 	help
 	  This enables support for DEC's MIPS based workstations.  For details
 	  see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
@@ -468,6 +469,7 @@ config SGI_IP22
 	select SYS_SUPPORTS_32BIT_KERNEL
 	select SYS_SUPPORTS_64BIT_KERNEL
 	select SYS_SUPPORTS_BIG_ENDIAN
+	select MIPS_L1_CACHE_SHIFT_7
 	help
 	  This are the SGI Indy, Challenge S and Indigo2, as well as certain
 	  OEM variants like the Tandem CMN B006S. To compile a Linux kernel
@@ -488,6 +490,7 @@ config SGI_IP27
 	select SYS_SUPPORTS_BIG_ENDIAN
 	select SYS_SUPPORTS_NUMA
 	select SYS_SUPPORTS_SMP
+	select MIPS_L1_CACHE_SHIFT_7
 	help
 	  This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
 	  workstations.  To compile a Linux kernel that runs on these, say Y
@@ -694,6 +697,7 @@ config MIKROTIK_RB532
 	select SWAP_IO_SPACE
 	select BOOT_RAW
 	select ARCH_REQUIRE_GPIOLIB
+	select MIPS_L1_CACHE_SHIFT_4
 	help
 	  Support the Mikrotik(tm) RouterBoard 532 series,
 	  based on the IDT RC32434 SoC.
@@ -1088,6 +1092,18 @@ config FW_SNIPROM
 config BOOT_ELF32
 	bool
 
+config MIPS_L1_CACHE_SHIFT_4
+	bool
+
+config MIPS_L1_CACHE_SHIFT_5
+	def_bool y
+
+config MIPS_L1_CACHE_SHIFT_6
+	bool
+
+config MIPS_L1_CACHE_SHIFT_7
+	bool
+
 config MIPS_L1_CACHE_SHIFT
 	int
 	default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
@@ -1372,6 +1388,7 @@ config CPU_CAVIUM_OCTEON
 	select LIBFDT
 	select USE_OF
 	select USB_EHCI_BIG_ENDIAN_MMIO
+	select MIPS_L1_CACHE_SHIFT_7
 	help
 	  The Cavium Octeon processor is a highly integrated chip containing
 	  many ethernet hardware widgets for networking tasks. The processor
@@ -1794,6 +1811,7 @@ config IP22_CPU_SCACHE
 config MIPS_CPU_SCACHE
 	bool
 	select BOARD_SCACHE
+	select MIPS_L1_CACHE_SHIFT_6
 
 config R5000_CPU_SCACHE
 	bool
diff --git a/arch/mips/pmcs-msp71xx/Kconfig b/arch/mips/pmcs-msp71xx/Kconfig
index 3482b8c..6073ca4 100644
--- a/arch/mips/pmcs-msp71xx/Kconfig
+++ b/arch/mips/pmcs-msp71xx/Kconfig
@@ -6,6 +6,7 @@ config PMC_MSP4200_EVAL
 	bool "PMC-Sierra MSP4200 Eval Board"
 	select IRQ_MSP_SLP
 	select HW_HAS_PCI
+	select MIPS_L1_CACHE_SHIFT_4
 
 config PMC_MSP4200_GW
 	bool "PMC-Sierra MSP4200 VoIP Gateway"
diff --git a/arch/mips/ralink/Kconfig b/arch/mips/ralink/Kconfig
index 424f034..1bfd1c1 100644
--- a/arch/mips/ralink/Kconfig
+++ b/arch/mips/ralink/Kconfig
@@ -15,6 +15,7 @@ choice
 
 	config SOC_RT288X
 		bool "RT288x"
+		select MIPS_L1_CACHE_SHIFT_4
 
 	config SOC_RT305X
 		bool "RT305x"
-- 
1.8.3.2

[PATCH 2/3] MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N>

[Florian Fainelli]

All platforms that require a special MIPS_L1_CACHE_SHIFT value have been
updated, such that we can now make MIPS_L1_CACHE_SHIFT default to the
appropriate integer value based on the select MIPS_L1_CACHE_SHIFT_<N>
variable.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
 arch/mips/Kconfig | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 753c5a3..123f7c0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1106,10 +1106,10 @@ config MIPS_L1_CACHE_SHIFT_7
 
 config MIPS_L1_CACHE_SHIFT
 	int
-	default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
-	default "6" if MIPS_CPU_SCACHE
-	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
-	default "5"
+	default "4" if MIPS_L1_CACHE_SHIFT_4
+	default "6" if MIPS_L1_CACHE_SHIFT_6
+	default "7" if MIPS_L1_CACHE_SHIFT_7
+	default "5" if MIPS_L1_CACHE_SHIFT_5
 
 config HAVE_STD_PC_SERIAL_PORT
 	bool
-- 
1.8.3.2

[PATCH 2/3] MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N>

[Florian Fainelli]

All platforms that require a special MIPS_L1_CACHE_SHIFT value have been
updated, such that we can now make MIPS_L1_CACHE_SHIFT default to the
appropriate integer value based on the select MIPS_L1_CACHE_SHIFT_<N>
variable.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
 arch/mips/Kconfig | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 753c5a3..123f7c0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1106,10 +1106,10 @@ config MIPS_L1_CACHE_SHIFT_7
 
 config MIPS_L1_CACHE_SHIFT
 	int
-	default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
-	default "6" if MIPS_CPU_SCACHE
-	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
-	default "5"
+	default "4" if MIPS_L1_CACHE_SHIFT_4
+	default "6" if MIPS_L1_CACHE_SHIFT_6
+	default "7" if MIPS_L1_CACHE_SHIFT_7
+	default "5" if MIPS_L1_CACHE_SHIFT_5
 
 config HAVE_STD_PC_SERIAL_PORT
 	bool
-- 
1.8.3.2

[PATCH 3/3] MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value

[Florian Fainelli]

Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
value of 4) instead of the currently configured 32 bytes L1-cache line
size.

Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
 arch/mips/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 123f7c0..a3fec87 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -139,6 +139,7 @@ config BCM63XX
 	select SWAP_IO_SPACE
 	select ARCH_REQUIRE_GPIOLIB
 	select HAVE_CLK
+	select MIPS_L1_CACHE_SHIFT_4
 	help
 	 Support for BCM63XX based boards
 
-- 
1.8.3.2

[PATCH 3/3] MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value

[Florian Fainelli]

Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
value of 4) instead of the currently configured 32 bytes L1-cache line
size.

Reported-by: Daniel Gonzalez <dgcbueu@gmail.com>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
 arch/mips/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 123f7c0..a3fec87 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -139,6 +139,7 @@ config BCM63XX
 	select SWAP_IO_SPACE
 	select ARCH_REQUIRE_GPIOLIB
 	select HAVE_CLK
+	select MIPS_L1_CACHE_SHIFT_4
 	help
 	 Support for BCM63XX based boards
 
-- 
1.8.3.2

Re: [PATCH 1/3] MIPS: introduce MIPS_L1_CACHE_SHIFT_<N>

[Jonas Gorski]

On Fri, Jan 10, 2014 at 9:35 PM, Florian Fainelli <florian@openwrt.org> wrote:
> In order to avoid keeping an ever growing list of chips which need to
> select a specific MIPS_L1_CACHE_SHIFT value introduce multiple internal
> and non-exposed Kconfig symbols for the various MIPS_L1_CACHE_SHIFT
> values out there and update the relevant Kconfig symbols to select them.
>
> Signed-off-by: Florian Fainelli <florian@openwrt.org>
> ---
>  arch/mips/Kconfig              | 18 ++++++++++++++++++
>  arch/mips/pmcs-msp71xx/Kconfig |  1 +
>  arch/mips/ralink/Kconfig       |  1 +
>  3 files changed, 20 insertions(+)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 17cc7ff..753c5a3 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -183,6 +183,7 @@ config MACH_DECSTATION
>         select SYS_SUPPORTS_128HZ
>         select SYS_SUPPORTS_256HZ
>         select SYS_SUPPORTS_1024HZ
> +       select MIPS_L1_CACHE_SHIFT_4
>         help
>           This enables support for DEC's MIPS based workstations.  For details
>           see the Linux/MIPS FAQ on <http://www.linux-mips.org/> and the
> @@ -468,6 +469,7 @@ config SGI_IP22
>         select SYS_SUPPORTS_32BIT_KERNEL
>         select SYS_SUPPORTS_64BIT_KERNEL
>         select SYS_SUPPORTS_BIG_ENDIAN
> +       select MIPS_L1_CACHE_SHIFT_7
>         help
>           This are the SGI Indy, Challenge S and Indigo2, as well as certain
>           OEM variants like the Tandem CMN B006S. To compile a Linux kernel
> @@ -488,6 +490,7 @@ config SGI_IP27
>         select SYS_SUPPORTS_BIG_ENDIAN
>         select SYS_SUPPORTS_NUMA
>         select SYS_SUPPORTS_SMP
> +       select MIPS_L1_CACHE_SHIFT_7
>         help
>           This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics
>           workstations.  To compile a Linux kernel that runs on these, say Y
> @@ -694,6 +697,7 @@ config MIKROTIK_RB532
>         select SWAP_IO_SPACE
>         select BOOT_RAW
>         select ARCH_REQUIRE_GPIOLIB
> +       select MIPS_L1_CACHE_SHIFT_4
>         help
>           Support the Mikrotik(tm) RouterBoard 532 series,
>           based on the IDT RC32434 SoC.
> @@ -1088,6 +1092,18 @@ config FW_SNIPROM
>  config BOOT_ELF32
>         bool
>
> +config MIPS_L1_CACHE_SHIFT_4
> +       bool
> +
> +config MIPS_L1_CACHE_SHIFT_5
> +       def_bool y

Won't this cause two CACHE_SHIFT_X to be y for anyone selecting one
different from 5? Making this default to n and "5" the default default
is I think the better way.


Jonas

Re: [PATCH 3/3] MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value

[John Crispin]

On 10/01/14 21:35, Florian Fainelli wrote:
> Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
> value of 4) instead of the currently configured 32 bytes L1-cache line
> size.
>
> Reported-by: Daniel Gonzalez<dgcbueu@gmail.com>
> Signed-off-by: Florian Fainelli<florian@openwrt.org>
> ---
>   arch/mips/Kconfig | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 123f7c0..a3fec87 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -139,6 +139,7 @@ config BCM63XX
>   	select SWAP_IO_SPACE
>   	select ARCH_REQUIRE_GPIOLIB
>   	select HAVE_CLK
> +	select MIPS_L1_CACHE_SHIFT_4
>   	help
>   	 Support for BCM63XX based boards
>


Hi Florian,

why is this not part of 1/3

     John

Re: [PATCH 2/3] MIPS: update MIPS_L1_CACHE_SHIFT based on MIPS_L1_CACHE_SHIFT_<N>

[Jonas Gorski]

On Fri, Jan 10, 2014 at 9:35 PM, Florian Fainelli <florian@openwrt.org> wrote:
> All platforms that require a special MIPS_L1_CACHE_SHIFT value have been
> updated, such that we can now make MIPS_L1_CACHE_SHIFT default to the
> appropriate integer value based on the select MIPS_L1_CACHE_SHIFT_<N>
> variable.
>
> Signed-off-by: Florian Fainelli <florian@openwrt.org>
> ---
>  arch/mips/Kconfig | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index 753c5a3..123f7c0 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -1106,10 +1106,10 @@ config MIPS_L1_CACHE_SHIFT_7
>
>  config MIPS_L1_CACHE_SHIFT
>         int
> -       default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X
> -       default "6" if MIPS_CPU_SCACHE
> -       default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
> -       default "5"
> +       default "4" if MIPS_L1_CACHE_SHIFT_4
> +       default "6" if MIPS_L1_CACHE_SHIFT_6
> +       default "7" if MIPS_L1_CACHE_SHIFT_7
> +       default "5" if MIPS_L1_CACHE_SHIFT_5

Having MIPS_L1_CACHE_SHIFT_5 default n and a last default "5" without
any condition to allows this to be ordered, which looks IMHO a lot
nicer ;-)


Jonas

Re: [PATCH 3/3] MIPS: BCM63XX: select correct MIPS_L1_CACHE_SHIFT value

[Jonas Gorski]

On Sat, Jan 11, 2014 at 11:45 AM, John Crispin <blogic@openwrt.org> wrote:
> On 10/01/14 21:35, Florian Fainelli wrote:
>>
>> Broadcom BCM63xx DSL SoCs have a L1-cache line size of 16 bytes (shift
>> value of 4) instead of the currently configured 32 bytes L1-cache line
>> size.
>>
>> Reported-by: Daniel Gonzalez<dgcbueu@gmail.com>
>> Signed-off-by: Florian Fainelli<florian@openwrt.org>
>> ---
>>   arch/mips/Kconfig | 1 +
>>   1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
>> index 123f7c0..a3fec87 100644
>> --- a/arch/mips/Kconfig
>> +++ b/arch/mips/Kconfig
>> @@ -139,6 +139,7 @@ config BCM63XX
>>         select SWAP_IO_SPACE
>>         select ARCH_REQUIRE_GPIOLIB
>>         select HAVE_CLK
>> +       select MIPS_L1_CACHE_SHIFT_4
>>         help
>>          Support for BCM63XX based boards
>>
>
>
> Hi Florian,
>
> why is this not part of 1/3

Because 1/3 is a clean-up/refactoring patch, and this one is a fix
(note that BCM63XX did not appear in the default list for "4" in the
old code, so it defaulted to "5"). Mixing cleanup and fixes is just
bad style. ;)


Jonas