* [PATCH 1/9] MIPS OCTEON Add OCTEON3 to get cpu type
[not found] <1421046385-2535-1-git-send-email-abhishek.paliwal@aricent.com>
@ 2015-01-12 7:06 ` Abhishek Paliwal
2015-01-12 7:06 ` Abhishek Paliwal
2015-01-12 19:04 ` Aaro Koskinen
2015-01-12 7:06 ` [PATCH 2/9] MIPS OCTEON Enable use of FPU Abhishek Paliwal
` (3 subsequent siblings)
4 siblings, 2 replies; 13+ messages in thread
From: Abhishek Paliwal @ 2015-01-12 7:06 UTC (permalink / raw)
To: kexin.hao, bo.liu
Cc: Chandrakala.Chavva, rakesh.garg, Abhishek Paliwal,
Andreas Herrmann, linux-mips, David Daney, James Hogan, kvm,
Ralf Baechle
commit cd3f5389489146297eb2c11e4f9d1c4e8aaeb59f upstream
Otherwise __builtin_unreachable might be called.
Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7014/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Abhishek Paliwal <abhishek.paliwal@aricent.com>
---
arch/mips/include/asm/cpu-type.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 02f591b..19557ca 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -160,6 +160,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
+ case CPU_CAVIUM_OCTEON3:
#endif
#if defined(CONFIG_SYS_HAS_CPU_BMIPS32_3300) || \
--
1.8.1.4
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 1/9] MIPS OCTEON Add OCTEON3 to get cpu type
2015-01-12 7:06 ` [PATCH 1/9] MIPS OCTEON Add OCTEON3 to get cpu type Abhishek Paliwal
@ 2015-01-12 7:06 ` Abhishek Paliwal
2015-01-12 19:04 ` Aaro Koskinen
1 sibling, 0 replies; 13+ messages in thread
From: Abhishek Paliwal @ 2015-01-12 7:06 UTC (permalink / raw)
To: kexin.hao, bo.liu
Cc: Chandrakala.Chavva, rakesh.garg, Abhishek Paliwal,
Andreas Herrmann, linux-mips, David Daney, James Hogan, kvm,
Ralf Baechle
commit cd3f5389489146297eb2c11e4f9d1c4e8aaeb59f upstream
Otherwise __builtin_unreachable might be called.
Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: David Daney <ddaney.cavm@gmail.com>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7014/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Abhishek Paliwal <abhishek.paliwal@aricent.com>
---
arch/mips/include/asm/cpu-type.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/mips/include/asm/cpu-type.h b/arch/mips/include/asm/cpu-type.h
index 02f591b..19557ca 100644
--- a/arch/mips/include/asm/cpu-type.h
+++ b/arch/mips/include/asm/cpu-type.h
@@ -160,6 +160,7 @@ static inline int __pure __get_cpu_type(const int cpu_type)
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
+ case CPU_CAVIUM_OCTEON3:
#endif
#if defined(CONFIG_SYS_HAS_CPU_BMIPS32_3300) || \
--
1.8.1.4
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 1/9] MIPS OCTEON Add OCTEON3 to get cpu type
2015-01-12 7:06 ` [PATCH 1/9] MIPS OCTEON Add OCTEON3 to get cpu type Abhishek Paliwal
2015-01-12 7:06 ` Abhishek Paliwal
@ 2015-01-12 19:04 ` Aaro Koskinen
1 sibling, 0 replies; 13+ messages in thread
From: Aaro Koskinen @ 2015-01-12 19:04 UTC (permalink / raw)
To: Abhishek Paliwal
Cc: kexin.hao, bo.liu, Chandrakala.Chavva, rakesh.garg,
Andreas Herrmann, linux-mips, David Daney, James Hogan, kvm,
Ralf Baechle
On Mon, Jan 12, 2015 at 12:36:17PM +0530, Abhishek Paliwal wrote:
> commit cd3f5389489146297eb2c11e4f9d1c4e8aaeb59f upstream
If you want to avoid surprises by git automatically cc'ing public mailing
lists and people based on the commit log, please set sendmail.supresscc
to "all". For further information check the git documentation.
A.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 2/9] MIPS OCTEON Enable use of FPU
[not found] <1421046385-2535-1-git-send-email-abhishek.paliwal@aricent.com>
2015-01-12 7:06 ` [PATCH 1/9] MIPS OCTEON Add OCTEON3 to get cpu type Abhishek Paliwal
@ 2015-01-12 7:06 ` Abhishek Paliwal
2015-01-12 7:06 ` Abhishek Paliwal
2015-01-12 17:30 ` David Daney
2015-01-12 7:06 ` [PATCH 3/9] MIPS Add function get ebase cpunum Abhishek Paliwal
` (2 subsequent siblings)
4 siblings, 2 replies; 13+ messages in thread
From: Abhishek Paliwal @ 2015-01-12 7:06 UTC (permalink / raw)
To: kexin.hao, bo.liu
Cc: Chandrakala.Chavva, rakesh.garg, Abhishek Paliwal, David Daney,
Andreas Herrmann, linux-mips, James Hogan, kvm, Ralf Baechle
commit a36d8225bceba4b7be47ade34d175945f85cffbc upstream
Some versions of the assembler will not assemble CFC1 for OCTEON, so override the ISA for these.
Add r4k_fpu.o to handle low level FPU initialization.
Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to pick up more FPU support.
Get rid of "#define cpu_has_fpu 0"
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7006/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Abhishek Paliwal <abhishek.paliwal@aricent.com>
---
.../asm/mach-cavium-octeon/cpu-feature-overrides.h | 1 -
arch/mips/kernel/Makefile | 2 +-
arch/mips/kernel/branch.c | 6 +-
arch/mips/kernel/octeon_switch.S | 85 ++++++++++++++++------
arch/mips/kernel/r4k_switch.S | 3 +
arch/mips/math-emu/cp1emu.c | 12 ++-
6 files changed, 80 insertions(+), 29 deletions(-)
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 94ed063..cf80228 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -22,7 +22,6 @@
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 0
#define cpu_has_tx39_cache 0
-#define cpu_has_fpu 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 26c6175..f76cf1e 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -42,7 +42,7 @@ obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
-obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
+obj-$(CONFIG_CPU_CAVIUM_OCTEON) += r4k_fpu.o octeon_switch.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SMP_UP) += smp-up.o
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 4d78bf4..418865f 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -366,7 +366,11 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
case cop1_op:
preempt_disable();
if (is_fpu_owner())
- asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+ asm volatile(
+ ".set push\n"
+ "\t.set mips1\n"
+ "\tcfc1\t%0,$31\n"
+ "\t.set pop" : "=r" (fcr31));
else
fcr31 = current->thread.fpu.fcr31;
preempt_enable();
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index 029e002..0f1163a 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -10,24 +10,11 @@
* Copyright (C) 2000 MIPS Technologies, Inc.
* written by Carsten Langgaard, carstenl@mips.com
*/
-#include <asm/asm.h>
-#include <asm/cachectl.h>
-#include <asm/fpregdef.h>
-#include <asm/mipsregs.h>
-#include <asm/asm-offsets.h>
-#include <asm/pgtable-bits.h>
-#include <asm/regdef.h>
-#include <asm/stackframe.h>
-#include <asm/thread_info.h>
-
-#include <asm/asmmacro.h>
-
-/*
- * Offset to the current process status flags, the first 32 bytes of the
- * stack are not used.
- */
-#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
-
+#define USE_ALTERNATE_RESUME_IMPL 1
+ .set push
+ .set arch=mips64r2
+#include "r4k_switch.S"
+ .set pop
/*
* task_struct *resume(task_struct *prev, task_struct *next,
* struct thread_info *next_ti, int usedfpu)
@@ -39,7 +26,62 @@
LONG_S t1, THREAD_STATUS(a0)
cpu_save_nonscratch a0
LONG_S ra, THREAD_REG31(a0)
+ /*
+ * check if we need to save FPU registers
+ */
+ PTR_L t3, TASK_THREAD_INFO(a0)
+ LONG_L t0, TI_FLAGS(t3)
+ li t1, _TIF_USEDFPU
+ and t2, t0, t1
+ beqz t2, 1f
+ nor t1, zero, t1
+
+ and t0, t0, t1
+ LONG_S t0, TI_FLAGS(t3)
+ /*
+ * clear saved user stack CU1 bit
+ */
+ LONG_L t0, ST_OFF(t3)
+ li t1, ~ST0_CU1
+ and t0, t0, t1
+ LONG_S t0, ST_OFF(t3)
+
+ .set push
+ .set arch=mips64r2
+ fpu_save_double a0 t0 t1 # c0_status passed in t0
+ # clobbers t1
+
+ .set pop
+1:
+
+ /* check if we need to save COP2 registers */
+ PTR_L t2, TASK_THREAD_INFO(a0)
+ LONG_L t0, ST_OFF(t2)
+ bbit0 t0, 30, 1f
+
+ /* Disable COP2 in the stored process state */
+ li t1, ST0_CU2
+ xor t0, t1
+ LONG_S t0, ST_OFF(t2)
+
+ /* Enable COP2 so we can save it */
+ mfc0 t0, CP0_STATUS
+ or t0, t1
+ mtc0 t0, CP0_STATUS
+
+ /* Save COP2 */
+ daddu a0, THREAD_CP2
+ jal octeon_cop2_save
+ dsubu a0, THREAD_CP2
+
+ /* Disable COP2 now that we are done */
+ mfc0 t0, CP0_STATUS
+ li t1, ST0_CU2
+ xor t0, t1
+ mtc0 t0, CP0_STATUS
+
+1:
#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
/* Check if we need to store CVMSEG state */
mfc0 t0, $11,7 /* CvmMemCtl */
@@ -85,12 +127,7 @@
move $28, a2
cpu_restore_nonscratch a1
-#if (_THREAD_SIZE - 32) < 0x8000
- PTR_ADDIU t0, $28, _THREAD_SIZE - 32
-#else
- PTR_LI t0, _THREAD_SIZE - 32
- PTR_ADDU t0, $28
-#endif
+ PTR_ADDU t0, $28, _THREAD_SIZE - 32
set_saved_sp t0, t1, t2
mfc0 t1, CP0_STATUS /* Do we really need this? */
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index cc78dd9..8a4f9a5 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -28,6 +28,7 @@
*/
#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
+#ifndef USE_ALTERNATE_RESUME_IMPL
/*
* FPU context is saved iff the process has used it's FPU in the current
* time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user
@@ -119,6 +120,8 @@
jr ra
END(resume)
+#endif /* USE_ALTERNATE_RESUME_IMPL */
+
/*
* Save a thread's fp context.
*/
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 0b4e2e3..edb110c 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -559,7 +559,11 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
case mm_bc1t_op:
preempt_disable();
if (is_fpu_owner())
- asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+ asm volatile(
+ ".set push\n"
+ " .set mips1\n"
+ " cfc1 %0,$31\n"
+ " .set pop" : "=r" (fcr31));
else
fcr31 = current->thread.fpu.fcr31;
preempt_enable();
@@ -817,7 +821,11 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
if (insn.i_format.rs == bc_op) {
preempt_disable();
if (is_fpu_owner())
- asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+ asm volatile(
+ ".set push\n"
+ "\t.set mips1\n"
+ "\tcfc1\t%0,$31\n"
+ "\t.set pop" : "=r" (fcr31));
else
fcr31 = current->thread.fpu.fcr31;
preempt_enable();
--
1.8.1.4
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 2/9] MIPS OCTEON Enable use of FPU
2015-01-12 7:06 ` [PATCH 2/9] MIPS OCTEON Enable use of FPU Abhishek Paliwal
@ 2015-01-12 7:06 ` Abhishek Paliwal
2015-01-12 17:30 ` David Daney
1 sibling, 0 replies; 13+ messages in thread
From: Abhishek Paliwal @ 2015-01-12 7:06 UTC (permalink / raw)
To: kexin.hao, bo.liu
Cc: Chandrakala.Chavva, rakesh.garg, Abhishek Paliwal, David Daney,
Andreas Herrmann, linux-mips, James Hogan, kvm, Ralf Baechle
commit a36d8225bceba4b7be47ade34d175945f85cffbc upstream
Some versions of the assembler will not assemble CFC1 for OCTEON, so override the ISA for these.
Add r4k_fpu.o to handle low level FPU initialization.
Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to pick up more FPU support.
Get rid of "#define cpu_has_fpu 0"
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7006/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Abhishek Paliwal <abhishek.paliwal@aricent.com>
---
.../asm/mach-cavium-octeon/cpu-feature-overrides.h | 1 -
arch/mips/kernel/Makefile | 2 +-
arch/mips/kernel/branch.c | 6 +-
arch/mips/kernel/octeon_switch.S | 85 ++++++++++++++++------
arch/mips/kernel/r4k_switch.S | 3 +
arch/mips/math-emu/cp1emu.c | 12 ++-
6 files changed, 80 insertions(+), 29 deletions(-)
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index 94ed063..cf80228 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -22,7 +22,6 @@
#define cpu_has_3k_cache 0
#define cpu_has_4k_cache 0
#define cpu_has_tx39_cache 0
-#define cpu_has_fpu 0
#define cpu_has_counter 1
#define cpu_has_watch 1
#define cpu_has_divec 1
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 26c6175..f76cf1e 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -42,7 +42,7 @@ obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
-obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
+obj-$(CONFIG_CPU_CAVIUM_OCTEON) += r4k_fpu.o octeon_switch.o
obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_SMP_UP) += smp-up.o
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 4d78bf4..418865f 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -366,7 +366,11 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
case cop1_op:
preempt_disable();
if (is_fpu_owner())
- asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+ asm volatile(
+ ".set push\n"
+ "\t.set mips1\n"
+ "\tcfc1\t%0,$31\n"
+ "\t.set pop" : "=r" (fcr31));
else
fcr31 = current->thread.fpu.fcr31;
preempt_enable();
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
index 029e002..0f1163a 100644
--- a/arch/mips/kernel/octeon_switch.S
+++ b/arch/mips/kernel/octeon_switch.S
@@ -10,24 +10,11 @@
* Copyright (C) 2000 MIPS Technologies, Inc.
* written by Carsten Langgaard, carstenl@mips.com
*/
-#include <asm/asm.h>
-#include <asm/cachectl.h>
-#include <asm/fpregdef.h>
-#include <asm/mipsregs.h>
-#include <asm/asm-offsets.h>
-#include <asm/pgtable-bits.h>
-#include <asm/regdef.h>
-#include <asm/stackframe.h>
-#include <asm/thread_info.h>
-
-#include <asm/asmmacro.h>
-
-/*
- * Offset to the current process status flags, the first 32 bytes of the
- * stack are not used.
- */
-#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
-
+#define USE_ALTERNATE_RESUME_IMPL 1
+ .set push
+ .set arch=mips64r2
+#include "r4k_switch.S"
+ .set pop
/*
* task_struct *resume(task_struct *prev, task_struct *next,
* struct thread_info *next_ti, int usedfpu)
@@ -39,7 +26,62 @@
LONG_S t1, THREAD_STATUS(a0)
cpu_save_nonscratch a0
LONG_S ra, THREAD_REG31(a0)
+ /*
+ * check if we need to save FPU registers
+ */
+ PTR_L t3, TASK_THREAD_INFO(a0)
+ LONG_L t0, TI_FLAGS(t3)
+ li t1, _TIF_USEDFPU
+ and t2, t0, t1
+ beqz t2, 1f
+ nor t1, zero, t1
+
+ and t0, t0, t1
+ LONG_S t0, TI_FLAGS(t3)
+ /*
+ * clear saved user stack CU1 bit
+ */
+ LONG_L t0, ST_OFF(t3)
+ li t1, ~ST0_CU1
+ and t0, t0, t1
+ LONG_S t0, ST_OFF(t3)
+
+ .set push
+ .set arch=mips64r2
+ fpu_save_double a0 t0 t1 # c0_status passed in t0
+ # clobbers t1
+
+ .set pop
+1:
+
+ /* check if we need to save COP2 registers */
+ PTR_L t2, TASK_THREAD_INFO(a0)
+ LONG_L t0, ST_OFF(t2)
+ bbit0 t0, 30, 1f
+
+ /* Disable COP2 in the stored process state */
+ li t1, ST0_CU2
+ xor t0, t1
+ LONG_S t0, ST_OFF(t2)
+
+ /* Enable COP2 so we can save it */
+ mfc0 t0, CP0_STATUS
+ or t0, t1
+ mtc0 t0, CP0_STATUS
+
+ /* Save COP2 */
+ daddu a0, THREAD_CP2
+ jal octeon_cop2_save
+ dsubu a0, THREAD_CP2
+
+ /* Disable COP2 now that we are done */
+ mfc0 t0, CP0_STATUS
+ li t1, ST0_CU2
+ xor t0, t1
+ mtc0 t0, CP0_STATUS
+
+1:
#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
/* Check if we need to store CVMSEG state */
mfc0 t0, $11,7 /* CvmMemCtl */
@@ -85,12 +127,7 @@
move $28, a2
cpu_restore_nonscratch a1
-#if (_THREAD_SIZE - 32) < 0x8000
- PTR_ADDIU t0, $28, _THREAD_SIZE - 32
-#else
- PTR_LI t0, _THREAD_SIZE - 32
- PTR_ADDU t0, $28
-#endif
+ PTR_ADDU t0, $28, _THREAD_SIZE - 32
set_saved_sp t0, t1, t2
mfc0 t1, CP0_STATUS /* Do we really need this? */
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index cc78dd9..8a4f9a5 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -28,6 +28,7 @@
*/
#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
+#ifndef USE_ALTERNATE_RESUME_IMPL
/*
* FPU context is saved iff the process has used it's FPU in the current
* time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user
@@ -119,6 +120,8 @@
jr ra
END(resume)
+#endif /* USE_ALTERNATE_RESUME_IMPL */
+
/*
* Save a thread's fp context.
*/
diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
index 0b4e2e3..edb110c 100644
--- a/arch/mips/math-emu/cp1emu.c
+++ b/arch/mips/math-emu/cp1emu.c
@@ -559,7 +559,11 @@ int mm_isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
case mm_bc1t_op:
preempt_disable();
if (is_fpu_owner())
- asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+ asm volatile(
+ ".set push\n"
+ " .set mips1\n"
+ " cfc1 %0,$31\n"
+ " .set pop" : "=r" (fcr31));
else
fcr31 = current->thread.fpu.fcr31;
preempt_enable();
@@ -817,7 +821,11 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
if (insn.i_format.rs == bc_op) {
preempt_disable();
if (is_fpu_owner())
- asm volatile("cfc1\t%0,$31" : "=r" (fcr31));
+ asm volatile(
+ ".set push\n"
+ "\t.set mips1\n"
+ "\tcfc1\t%0,$31\n"
+ "\t.set pop" : "=r" (fcr31));
else
fcr31 = current->thread.fpu.fcr31;
preempt_enable();
--
1.8.1.4
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [PATCH 2/9] MIPS OCTEON Enable use of FPU
2015-01-12 7:06 ` [PATCH 2/9] MIPS OCTEON Enable use of FPU Abhishek Paliwal
2015-01-12 7:06 ` Abhishek Paliwal
@ 2015-01-12 17:30 ` David Daney
2015-01-12 17:30 ` David Daney
1 sibling, 1 reply; 13+ messages in thread
From: David Daney @ 2015-01-12 17:30 UTC (permalink / raw)
To: Abhishek Paliwal
Cc: kexin.hao, bo.liu, Chandrakala.Chavva, rakesh.garg, David Daney,
Andreas Herrmann, linux-mips, James Hogan, kvm, Ralf Baechle
On 01/11/2015 11:06 PM, Abhishek Paliwal wrote:
> commit a36d8225bceba4b7be47ade34d175945f85cffbc upstream
Why are you spamming us with this? We don't need to know what you are
cherry-picking.
>
> Some versions of the assembler will not assemble CFC1 for OCTEON, so override the ISA for these.
>
> Add r4k_fpu.o to handle low level FPU initialization.
>
> Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to pick up more FPU support.
>
> Get rid of "#define cpu_has_fpu 0"
>
> Signed-off-by: David Daney <david.daney@cavium.com>
> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
> Cc: linux-mips@linux-mips.org
> Cc: James Hogan <james.hogan@imgtec.com>
> Cc: kvm@vger.kernel.org
> Patchwork: https://patchwork.linux-mips.org/patch/7006/
> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
> Signed-off-by: Abhishek Paliwal <abhishek.paliwal@aricent.com>
> ---
> .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 1 -
> arch/mips/kernel/Makefile | 2 +-
> arch/mips/kernel/branch.c | 6 +-
> arch/mips/kernel/octeon_switch.S | 85 ++++++++++++++++------
> arch/mips/kernel/r4k_switch.S | 3 +
> arch/mips/math-emu/cp1emu.c | 12 ++-
> 6 files changed, 80 insertions(+), 29 deletions(-)
>
[...]
>
> "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
I wrote the patch, what gives you the right to say that it is "...
proprietary to Aricent ..."? Nothing. We really must insist that you
quit making this type of misrepresentation.
David Daney
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/9] MIPS OCTEON Enable use of FPU
2015-01-12 17:30 ` David Daney
@ 2015-01-12 17:30 ` David Daney
0 siblings, 0 replies; 13+ messages in thread
From: David Daney @ 2015-01-12 17:30 UTC (permalink / raw)
To: Abhishek Paliwal
Cc: kexin.hao, bo.liu, Chandrakala.Chavva, rakesh.garg, David Daney,
Andreas Herrmann, linux-mips, James Hogan, kvm, Ralf Baechle
On 01/11/2015 11:06 PM, Abhishek Paliwal wrote:
> commit a36d8225bceba4b7be47ade34d175945f85cffbc upstream
Why are you spamming us with this? We don't need to know what you are
cherry-picking.
>
> Some versions of the assembler will not assemble CFC1 for OCTEON, so override the ISA for these.
>
> Add r4k_fpu.o to handle low level FPU initialization.
>
> Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to pick up more FPU support.
>
> Get rid of "#define cpu_has_fpu 0"
>
> Signed-off-by: David Daney <david.daney@cavium.com>
> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
> Cc: linux-mips@linux-mips.org
> Cc: James Hogan <james.hogan@imgtec.com>
> Cc: kvm@vger.kernel.org
> Patchwork: https://patchwork.linux-mips.org/patch/7006/
> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
> Signed-off-by: Abhishek Paliwal <abhishek.paliwal@aricent.com>
> ---
> .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 1 -
> arch/mips/kernel/Makefile | 2 +-
> arch/mips/kernel/branch.c | 6 +-
> arch/mips/kernel/octeon_switch.S | 85 ++++++++++++++++------
> arch/mips/kernel/r4k_switch.S | 3 +
> arch/mips/math-emu/cp1emu.c | 12 ++-
> 6 files changed, 80 insertions(+), 29 deletions(-)
>
[...]
>
> "DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
I wrote the patch, what gives you the right to say that it is "...
proprietary to Aricent ..."? Nothing. We really must insist that you
quit making this type of misrepresentation.
David Daney
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 3/9] MIPS Add function get ebase cpunum
[not found] <1421046385-2535-1-git-send-email-abhishek.paliwal@aricent.com>
2015-01-12 7:06 ` [PATCH 1/9] MIPS OCTEON Add OCTEON3 to get cpu type Abhishek Paliwal
2015-01-12 7:06 ` [PATCH 2/9] MIPS OCTEON Enable use of FPU Abhishek Paliwal
@ 2015-01-12 7:06 ` Abhishek Paliwal
2015-01-12 7:06 ` Abhishek Paliwal
2015-01-12 7:06 ` [PATCH 4/9] MIPS Add minimal support for OCTEON3 to c-r4k.c Abhishek Paliwal
2015-01-12 7:06 ` [PATCH 5/9] MIPS donot build fast TLB refill handler with 32-bit kernels Abhishek Paliwal
4 siblings, 1 reply; 13+ messages in thread
From: Abhishek Paliwal @ 2015-01-12 7:06 UTC (permalink / raw)
To: kexin.hao, bo.liu
Cc: Chandrakala.Chavva, rakesh.garg, Abhishek Paliwal, David Daney,
Andreas Herrmann, linux-mips, James Hogan, kvm, Ralf Baechle
commit 45b585c8dcdc469bb40b58cc2801acd7a2332525 upstream
This returns the CPUNum from the low order Ebase bits.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7012/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Abhishek Paliwal <abhishek.paliwal@aricent.com>
---
arch/mips/include/asm/mipsregs.h | 8 ++++++++
arch/mips/kernel/cpu-probe.c | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bbc3dd4..327f989 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1894,6 +1894,14 @@ __BUILD_SET_C0(brcm_cmt_ctrl)
__BUILD_SET_C0(brcm_config)
__BUILD_SET_C0(brcm_mode)
+/*
+ * Return low 10 bits of ebase.
+ * Note that under KVM (MIPSVZ) this returns vcpu id.
+ */
+static inline unsigned int get_ebase_cpunum(void)
+{
+ return read_c0_ebase() & 0x3ff;
+}
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_MIPSREGS_H */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 530f832..19432da 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -399,7 +399,7 @@ static void decode_configs(struct cpuinfo_mips *c)
mips_probe_watch_registers(c);
if (cpu_has_mips_r2)
- c->core = read_c0_ebase() & 0x3ff;
+ c->core = get_ebase_cpunum();
}
#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
--
1.8.1.4
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 3/9] MIPS Add function get ebase cpunum
2015-01-12 7:06 ` [PATCH 3/9] MIPS Add function get ebase cpunum Abhishek Paliwal
@ 2015-01-12 7:06 ` Abhishek Paliwal
0 siblings, 0 replies; 13+ messages in thread
From: Abhishek Paliwal @ 2015-01-12 7:06 UTC (permalink / raw)
To: kexin.hao, bo.liu
Cc: Chandrakala.Chavva, rakesh.garg, Abhishek Paliwal, David Daney,
Andreas Herrmann, linux-mips, James Hogan, kvm, Ralf Baechle
commit 45b585c8dcdc469bb40b58cc2801acd7a2332525 upstream
This returns the CPUNum from the low order Ebase bits.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7012/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Abhishek Paliwal <abhishek.paliwal@aricent.com>
---
arch/mips/include/asm/mipsregs.h | 8 ++++++++
arch/mips/kernel/cpu-probe.c | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index bbc3dd4..327f989 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1894,6 +1894,14 @@ __BUILD_SET_C0(brcm_cmt_ctrl)
__BUILD_SET_C0(brcm_config)
__BUILD_SET_C0(brcm_mode)
+/*
+ * Return low 10 bits of ebase.
+ * Note that under KVM (MIPSVZ) this returns vcpu id.
+ */
+static inline unsigned int get_ebase_cpunum(void)
+{
+ return read_c0_ebase() & 0x3ff;
+}
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_MIPSREGS_H */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 530f832..19432da 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -399,7 +399,7 @@ static void decode_configs(struct cpuinfo_mips *c)
mips_probe_watch_registers(c);
if (cpu_has_mips_r2)
- c->core = read_c0_ebase() & 0x3ff;
+ c->core = get_ebase_cpunum();
}
#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
--
1.8.1.4
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 4/9] MIPS Add minimal support for OCTEON3 to c-r4k.c
[not found] <1421046385-2535-1-git-send-email-abhishek.paliwal@aricent.com>
` (2 preceding siblings ...)
2015-01-12 7:06 ` [PATCH 3/9] MIPS Add function get ebase cpunum Abhishek Paliwal
@ 2015-01-12 7:06 ` Abhishek Paliwal
2015-01-12 7:06 ` Abhishek Paliwal
2015-01-12 7:06 ` [PATCH 5/9] MIPS donot build fast TLB refill handler with 32-bit kernels Abhishek Paliwal
4 siblings, 1 reply; 13+ messages in thread
From: Abhishek Paliwal @ 2015-01-12 7:06 UTC (permalink / raw)
To: kexin.hao, bo.liu
Cc: Chandrakala.Chavva, rakesh.garg, Abhishek Paliwal, David Daney,
Andreas Herrmann, linux-mips, James Hogan, kvm, Ralf Baechle
commit 18a8cd63c0d800bbc8b91f03054fcb13d308f6ec upstream
These are needed to boot a generic mips64r2 kernel on OCTEONIII.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7003/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Abhishek Paliwal <abhishek.paliwal@aricent.com>
---
arch/mips/include/asm/r4kcache.h | 2 ++
arch/mips/mm/c-r4k.c | 47 ++++++++++++++++++++++++++++++++++++----
2 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index c84cadd..3be43ca 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -420,6 +420,8 @@ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32,
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index bc941f8..15dfc4a 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -109,18 +109,33 @@ static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
blast_dcache64_page(addr);
}
+static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
+{
+ blast_dcache128_page(addr);
+}
+
static void r4k_blast_dcache_page_setup(void)
{
unsigned long dc_lsize = cpu_dcache_line_size();
- if (dc_lsize == 0)
+ switch (dc_lsize) {
+ case 0:
r4k_blast_dcache_page = (void *)cache_noop;
- else if (dc_lsize == 16)
+ break;
+ case 16:
r4k_blast_dcache_page = blast_dcache16_page;
- else if (dc_lsize == 32)
+ break;
+ case 32:
r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
- else if (dc_lsize == 64)
+ break;
+ case 64:
r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
+ break;
+ case 128:
+ r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
+ break;
+ default:
+ break;
}
static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
@@ -137,6 +152,8 @@ static void r4k_blast_dcache_page_indexed_setup(void)
r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
else if (dc_lsize == 64)
r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
+ else if (dc_lsize == 128)
+ r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
}
void (* r4k_blast_dcache)(void);
@@ -154,6 +171,8 @@ static void r4k_blast_dcache_setup(void)
r4k_blast_dcache = blast_dcache32;
else if (dc_lsize == 64)
r4k_blast_dcache = blast_dcache64;
+ else if (dc_lsize == 128)
+ r4k_blast_dcache = blast_dcache128;
}
/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
@@ -243,6 +262,8 @@ static void r4k_blast_icache_page_setup(void)
r4k_blast_icache_page = blast_icache32_page;
else if (ic_lsize == 64)
r4k_blast_icache_page = blast_icache64_page;
+ else if (ic_lsize == 128)
+ r4k_blast_icache_page = blast_icache128_page;
}
@@ -295,6 +316,8 @@ static void r4k_blast_icache_setup(void)
r4k_blast_icache = blast_icache32;
} else if (ic_lsize == 64)
r4k_blast_icache = blast_icache64;
+ else if (ic_lsize == 128)
+ r4k_blast_icache = blast_icache128;
}
static void (* r4k_blast_scache_page)(unsigned long addr);
@@ -1010,6 +1033,21 @@ static void probe_pcache(void)
c->dcache.waybit = 0;
break;
+ case CPU_CAVIUM_OCTEON3:
+ /* For now lie about the number of ways. */
+ c->icache.linesz = 128;
+ c->icache.sets = 16;
+ c->icache.ways = 8;
+ c->icache.flags |= MIPS_CACHE_VTAG;
+ icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
+
+ c->dcache.linesz = 128;
+ c->dcache.ways = 8;
+ c->dcache.sets = 8;
+ dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
+ c->options |= MIPS_CPU_PREFETCH;
+ break;
+
default:
if (!(config & MIPS_CONF_M))
panic("Don't know how to probe P-caches on this cpu.");
@@ -1291,6 +1329,7 @@ static void setup_scache(void)
loongson2_sc_init();
return;
+ case CPU_CAVIUM_OCTEON3:
case CPU_XLP:
/* don't need to worry about L2, fully coherent */
return;
--
1.8.1.4
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 4/9] MIPS Add minimal support for OCTEON3 to c-r4k.c
2015-01-12 7:06 ` [PATCH 4/9] MIPS Add minimal support for OCTEON3 to c-r4k.c Abhishek Paliwal
@ 2015-01-12 7:06 ` Abhishek Paliwal
0 siblings, 0 replies; 13+ messages in thread
From: Abhishek Paliwal @ 2015-01-12 7:06 UTC (permalink / raw)
To: kexin.hao, bo.liu
Cc: Chandrakala.Chavva, rakesh.garg, Abhishek Paliwal, David Daney,
Andreas Herrmann, linux-mips, James Hogan, kvm, Ralf Baechle
commit 18a8cd63c0d800bbc8b91f03054fcb13d308f6ec upstream
These are needed to boot a generic mips64r2 kernel on OCTEONIII.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7003/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Abhishek Paliwal <abhishek.paliwal@aricent.com>
---
arch/mips/include/asm/r4kcache.h | 2 ++
arch/mips/mm/c-r4k.c | 47 ++++++++++++++++++++++++++++++++++++----
2 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h
index c84cadd..3be43ca 100644
--- a/arch/mips/include/asm/r4kcache.h
+++ b/arch/mips/include/asm/r4kcache.h
@@ -420,6 +420,8 @@ __BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32,
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64, )
+__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
+__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 128, )
__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128, )
__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index bc941f8..15dfc4a 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -109,18 +109,33 @@ static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
blast_dcache64_page(addr);
}
+static inline void r4k_blast_dcache_page_dc128(unsigned long addr)
+{
+ blast_dcache128_page(addr);
+}
+
static void r4k_blast_dcache_page_setup(void)
{
unsigned long dc_lsize = cpu_dcache_line_size();
- if (dc_lsize == 0)
+ switch (dc_lsize) {
+ case 0:
r4k_blast_dcache_page = (void *)cache_noop;
- else if (dc_lsize == 16)
+ break;
+ case 16:
r4k_blast_dcache_page = blast_dcache16_page;
- else if (dc_lsize == 32)
+ break;
+ case 32:
r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
- else if (dc_lsize == 64)
+ break;
+ case 64:
r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
+ break;
+ case 128:
+ r4k_blast_dcache_page = r4k_blast_dcache_page_dc128;
+ break;
+ default:
+ break;
}
static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
@@ -137,6 +152,8 @@ static void r4k_blast_dcache_page_indexed_setup(void)
r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
else if (dc_lsize == 64)
r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
+ else if (dc_lsize == 128)
+ r4k_blast_dcache_page_indexed = blast_dcache128_page_indexed;
}
void (* r4k_blast_dcache)(void);
@@ -154,6 +171,8 @@ static void r4k_blast_dcache_setup(void)
r4k_blast_dcache = blast_dcache32;
else if (dc_lsize == 64)
r4k_blast_dcache = blast_dcache64;
+ else if (dc_lsize == 128)
+ r4k_blast_dcache = blast_dcache128;
}
/* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
@@ -243,6 +262,8 @@ static void r4k_blast_icache_page_setup(void)
r4k_blast_icache_page = blast_icache32_page;
else if (ic_lsize == 64)
r4k_blast_icache_page = blast_icache64_page;
+ else if (ic_lsize == 128)
+ r4k_blast_icache_page = blast_icache128_page;
}
@@ -295,6 +316,8 @@ static void r4k_blast_icache_setup(void)
r4k_blast_icache = blast_icache32;
} else if (ic_lsize == 64)
r4k_blast_icache = blast_icache64;
+ else if (ic_lsize == 128)
+ r4k_blast_icache = blast_icache128;
}
static void (* r4k_blast_scache_page)(unsigned long addr);
@@ -1010,6 +1033,21 @@ static void probe_pcache(void)
c->dcache.waybit = 0;
break;
+ case CPU_CAVIUM_OCTEON3:
+ /* For now lie about the number of ways. */
+ c->icache.linesz = 128;
+ c->icache.sets = 16;
+ c->icache.ways = 8;
+ c->icache.flags |= MIPS_CACHE_VTAG;
+ icache_size = c->icache.sets * c->icache.ways * c->icache.linesz;
+
+ c->dcache.linesz = 128;
+ c->dcache.ways = 8;
+ c->dcache.sets = 8;
+ dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz;
+ c->options |= MIPS_CPU_PREFETCH;
+ break;
+
default:
if (!(config & MIPS_CONF_M))
panic("Don't know how to probe P-caches on this cpu.");
@@ -1291,6 +1329,7 @@ static void setup_scache(void)
loongson2_sc_init();
return;
+ case CPU_CAVIUM_OCTEON3:
case CPU_XLP:
/* don't need to worry about L2, fully coherent */
return;
--
1.8.1.4
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 5/9] MIPS donot build fast TLB refill handler with 32-bit kernels.
[not found] <1421046385-2535-1-git-send-email-abhishek.paliwal@aricent.com>
` (3 preceding siblings ...)
2015-01-12 7:06 ` [PATCH 4/9] MIPS Add minimal support for OCTEON3 to c-r4k.c Abhishek Paliwal
@ 2015-01-12 7:06 ` Abhishek Paliwal
2015-01-12 7:06 ` Abhishek Paliwal
4 siblings, 1 reply; 13+ messages in thread
From: Abhishek Paliwal @ 2015-01-12 7:06 UTC (permalink / raw)
To: kexin.hao, bo.liu
Cc: Chandrakala.Chavva, rakesh.garg, Abhishek Paliwal, David Daney,
Andreas Herrmann, linux-mips, James Hogan, kvm, Ralf Baechle
commit 35d0470668cca234e49ed35342b3f9a0eec8355c upstream
The fast handler only supports 64-bit kernels.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7010/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Abhishek Paliwal <abhishek.paliwal@aricent.com>
---
arch/mips/mm/tlbex.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index aa24119..c05f2fd 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1247,13 +1247,17 @@ static void build_r4000_tlb_refill_handler(void)
unsigned int final_len;
struct mips_huge_tlb_info htlb_info __maybe_unused;
enum vmalloc64_mode vmalloc_mode __maybe_unused;
-
+#ifdef CONFIG_64BIT
+ bool is64bit = true;
+#else
+ bool is64bit = false;
+#endif
memset(tlb_handler, 0, sizeof(tlb_handler));
memset(labels, 0, sizeof(labels));
memset(relocs, 0, sizeof(relocs));
memset(final_handler, 0, sizeof(final_handler));
- if ((scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
+ if (is64bit && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
scratch_reg);
vmalloc_mode = refill_scratch;
--
1.8.1.4
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
^ permalink raw reply related [flat|nested] 13+ messages in thread* [PATCH 5/9] MIPS donot build fast TLB refill handler with 32-bit kernels.
2015-01-12 7:06 ` [PATCH 5/9] MIPS donot build fast TLB refill handler with 32-bit kernels Abhishek Paliwal
@ 2015-01-12 7:06 ` Abhishek Paliwal
0 siblings, 0 replies; 13+ messages in thread
From: Abhishek Paliwal @ 2015-01-12 7:06 UTC (permalink / raw)
To: kexin.hao, bo.liu
Cc: Chandrakala.Chavva, rakesh.garg, Abhishek Paliwal, David Daney,
Andreas Herrmann, linux-mips, James Hogan, kvm, Ralf Baechle
commit 35d0470668cca234e49ed35342b3f9a0eec8355c upstream
The fast handler only supports 64-bit kernels.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7010/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Abhishek Paliwal <abhishek.paliwal@aricent.com>
---
arch/mips/mm/tlbex.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index aa24119..c05f2fd 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -1247,13 +1247,17 @@ static void build_r4000_tlb_refill_handler(void)
unsigned int final_len;
struct mips_huge_tlb_info htlb_info __maybe_unused;
enum vmalloc64_mode vmalloc_mode __maybe_unused;
-
+#ifdef CONFIG_64BIT
+ bool is64bit = true;
+#else
+ bool is64bit = false;
+#endif
memset(tlb_handler, 0, sizeof(tlb_handler));
memset(labels, 0, sizeof(labels));
memset(relocs, 0, sizeof(relocs));
memset(final_handler, 0, sizeof(final_handler));
- if ((scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
+ if (is64bit && (scratch_reg >= 0 || scratchpad_available()) && use_bbit_insns()) {
htlb_info = build_fast_tlb_refill_handler(&p, &l, &r, K0, K1,
scratch_reg);
vmalloc_mode = refill_scratch;
--
1.8.1.4
"DISCLAIMER: This message is proprietary to Aricent and is intended solely for the use of the individual to whom it is addressed. It may contain privileged or confidential information and should not be circulated or used for any purpose other than for what it is intended. If you have received this message in error, please notify the originator immediately. If you are not the intended recipient, you are notified that you are strictly prohibited from using, copying, altering, or disclosing the contents of this message. Aricent accepts no responsibility for loss or damage arising from the use of the information transmitted by this email including damage from virus."
^ permalink raw reply related [flat|nested] 13+ messages in thread