Re: [PATCH RFC v2 40/70] MIPS: mm: page: Add MIPS R6 support

[Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>]

Hello.

On 1/16/2015 1:49 PM, Markos Chandras wrote:

> The MIPS R6 pref instruction only have 9 bits for the immediate
> field so skip the micro-assembler PREF instruction is the offset
> does not fit in 9 bits.

> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> ---
>   arch/mips/mm/page.c | 20 +++++++++++++++++---
>   1 file changed, 17 insertions(+), 3 deletions(-)

> diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
> index b611102e23b5..b84e0b2ce140 100644
> --- a/arch/mips/mm/page.c
> +++ b/arch/mips/mm/page.c
> @@ -72,6 +72,20 @@ static struct uasm_reloc relocs[5];
>   #define cpu_is_r4600_v1_x()	((read_c0_prid() & 0xfffffff0) == 0x00002010)
>   #define cpu_is_r4600_v2_x()	((read_c0_prid() & 0xfffffff0) == 0x00002020)
>
> +/*
> + * R6 has a limited offset of the pref instruction.
> + * Skip it if the offset is more than 9 bits.
> + */
> +#define _uasm_i_pref(a, b, c, d)		\
> +do {						\
> +	if (cpu_has_mips_r6) {			\
> +	    if ((d > 0xff) || (d < -0x100))	\

    Please indent with tabs only. Inner () not necessary. And it looks like 
you've reversed the conditions.

> +		uasm_i_pref(a, b, c, d);	\
> +	} else {				\
> +		uasm_i_pref(a, b, c, d);	\
> +	}					\
> +} while(0)
> +
[...]

WBR, Sergei