Re: [PATCH RFC v2 27/70] MIPS: kernel: cevt-r4k: Add MIPS R6 to the c0_compare_interrupt handler

[James Hogan <james.hogan@imgtec.com>]

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Hi Maciej,

On Tue, Jan 20, 2015 at 01:22:24AM +0000, Maciej W. Rozycki wrote:
> On Fri, 16 Jan 2015, Markos Chandras wrote:
> 
> > From: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> > 
> > Just like MIPS R2, in MIPS R6 it is possible to determine if a
> > timer interrupt has happened or not.
> > 
> > Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
> > Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> > ---
> 
>  While a preexisting bug, this is simply not true, there's CP0.Cause.TI to 
> examine for a timer interrupt pending.  Please fix your change to use 
> `c0_compare_int_pending' instead and synchronise with stuff posted by 
> James (cc-ed) at <http://patchwork.linux-mips.org/patch/8900/>.

I'm not sure I follow what you mean. This change makes it treat r6 like
it treats r2 (i.e. there is still a Cause.TI bit), which sounds correct
to me. I'm guessing cpu_has_mips_r6 doesn't imply cpu_has_mips_r2.

Cheers
James

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