Linux MIPS Architecture development
 help / color / mirror / Atom feed
From: James Hogan <james.hogan@imgtec.com>
To: Paul Burton <paul.burton@imgtec.com>, <linux-mips@linux-mips.org>
Cc: Lars-Peter Clausen <lars@metafoo.de>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH v4 13/37] MIPS: JZ4740: register an irq_domain for the interrupt controller
Date: Tue, 28 Apr 2015 11:46:04 +0100	[thread overview]
Message-ID: <553F64EC.8040602@imgtec.com> (raw)
In-Reply-To: <1429881457-16016-14-git-send-email-paul.burton@imgtec.com>

[-- Attachment #1: Type: text/plain, Size: 1583 bytes --]

Hi Paul,

On 24/04/15 14:17, Paul Burton wrote:
> When probining the interrupt controller, register an IRQ domain such

probining?

Cheers
James

> that the interrupts can be translated by devicetree code & thus used
> from devicetree.
> 
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> Cc: Lars-Peter Clausen <lars@metafoo.de>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org
> ---
> Changes in v4:
>   - None.
> 
> Changes in v3:
>   - Rebase.
> 
> Changes in v2:
>   - None.
> ---
>  arch/mips/jz4740/irq.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
> index ed51915..ddcf78a 100644
> --- a/arch/mips/jz4740/irq.c
> +++ b/arch/mips/jz4740/irq.c
> @@ -85,6 +85,7 @@ static int __init jz4740_intc_of_init(struct device_node *node,
>  {
>  	struct irq_chip_generic *gc;
>  	struct irq_chip_type *ct;
> +	struct irq_domain *domain;
>  	int parent_irq;
>  
>  	parent_irq = irq_of_parse_and_map(node, 0);
> @@ -113,6 +114,11 @@ static int __init jz4740_intc_of_init(struct device_node *node,
>  
>  	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
>  
> +	domain = irq_domain_add_legacy(node, num_chips * 32, JZ4740_IRQ_BASE, 0,
> +				       &irq_domain_simple_ops, NULL);
> +	if (!domain)
> +		pr_warn("unable to register IRQ domain\n");
> +
>  	setup_irq(parent_irq, &jz4740_cascade_action);
>  	return 0;
>  }
> 


[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

WARNING: multiple messages have this Message-ID (diff)
From: James Hogan <james.hogan@imgtec.com>
To: Paul Burton <paul.burton@imgtec.com>, linux-mips@linux-mips.org
Cc: Lars-Peter Clausen <lars@metafoo.de>,
	Thomas Gleixner <tglx@linutronix.de>,
	Jason Cooper <jason@lakedaemon.net>,
	Ralf Baechle <ralf@linux-mips.org>
Subject: Re: [PATCH v4 13/37] MIPS: JZ4740: register an irq_domain for the interrupt controller
Date: Tue, 28 Apr 2015 11:46:04 +0100	[thread overview]
Message-ID: <553F64EC.8040602@imgtec.com> (raw)
Message-ID: <20150428104604.Ncm8ZKmybCm65xsRa6WnOKliVlLNl1M4zphuDwCCNRg@z> (raw)
In-Reply-To: <1429881457-16016-14-git-send-email-paul.burton@imgtec.com>

[-- Attachment #1: Type: text/plain, Size: 1583 bytes --]

Hi Paul,

On 24/04/15 14:17, Paul Burton wrote:
> When probining the interrupt controller, register an IRQ domain such

probining?

Cheers
James

> that the interrupts can be translated by devicetree code & thus used
> from devicetree.
> 
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> Cc: Lars-Peter Clausen <lars@metafoo.de>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Jason Cooper <jason@lakedaemon.net>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org
> ---
> Changes in v4:
>   - None.
> 
> Changes in v3:
>   - Rebase.
> 
> Changes in v2:
>   - None.
> ---
>  arch/mips/jz4740/irq.c | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
> index ed51915..ddcf78a 100644
> --- a/arch/mips/jz4740/irq.c
> +++ b/arch/mips/jz4740/irq.c
> @@ -85,6 +85,7 @@ static int __init jz4740_intc_of_init(struct device_node *node,
>  {
>  	struct irq_chip_generic *gc;
>  	struct irq_chip_type *ct;
> +	struct irq_domain *domain;
>  	int parent_irq;
>  
>  	parent_irq = irq_of_parse_and_map(node, 0);
> @@ -113,6 +114,11 @@ static int __init jz4740_intc_of_init(struct device_node *node,
>  
>  	irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);
>  
> +	domain = irq_domain_add_legacy(node, num_chips * 32, JZ4740_IRQ_BASE, 0,
> +				       &irq_domain_simple_ops, NULL);
> +	if (!domain)
> +		pr_warn("unable to register IRQ domain\n");
> +
>  	setup_irq(parent_irq, &jz4740_cascade_action);
>  	return 0;
>  }
> 


[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

  parent reply	other threads:[~2015-04-28 10:46 UTC|newest]

Thread overview: 101+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-04-24 13:17 [PATCH v4 00/37] JZ4780 & CI20 support Paul Burton
2015-04-24 13:17 ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 01/37] devicetree/bindings: add Ingenic Semiconductor vendor prefix Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 02/37] devicetree/bindings: add Qi Hardware " Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 03/37] MIPS: JZ4740: introduce CONFIG_MACH_INGENIC Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 04/37] MIPS: ingenic: add newer vendor IDs Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 05/37] MIPS: JZ4740: require & include DT Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 06/37] MIPS: irq_cpu: declare irqchip table entry Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 07/37] MIPS: JZ4740: probe CPU interrupt controller via DT Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 08/37] MIPS: JZ4740: use generic plat_irq_dispatch Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 09/37] MIPS: JZ4740: move arch_init_irq out of arch/mips/jz4740/irq.c Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 10/37] devicetree: document Ingenic SoC interrupt controller binding Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 11/37] MIPS: JZ4740: probe interrupt controller via DT Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 12/37] MIPS: JZ4740: parse SoC interrupt controller parent IRQ from DT Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 13/37] MIPS: JZ4740: register an irq_domain for the interrupt controller Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-28 10:46   ` James Hogan [this message]
2015-04-28 10:46     ` James Hogan
2015-04-24 13:17 ` [PATCH v4 14/37] MIPS: JZ4740: drop intc debugfs code Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-28  7:20   ` Lars-Peter Clausen
2015-04-24 13:17 ` [PATCH v4 15/37] MIPS: JZ4740: remove jz_intc_base global Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-27 22:35   ` James Hogan
2015-04-27 22:35     ` James Hogan
2015-04-24 13:17 ` [PATCH v4 16/37] MIPS: JZ4740: support >32 interrupts Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 17/37] MIPS: JZ4740: define IRQ numbers based on number of intc IRQs Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 18/37] MIPS: JZ4740: read intc base address from DT Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 19/37] MIPS: JZ4740: avoid JZ4740-specific naming Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 20/37] MIPS: JZ4740: support newer SoC interrupt controllers Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-28 11:03   ` James Hogan
2015-04-28 11:03     ` James Hogan
2015-04-24 13:17 ` [PATCH v4 21/37] irqchip: move Ingenic SoC intc driver to drivers/irqchip Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 22/37] MIPS: JZ4740: call jz4740_clock_init earlier Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 23/37] MIPS: JZ4740: replace use of jz4740_clock_bdata Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 24/37] devicetree: add Ingenic CGU binding documentation Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 25/37] clk: ingenic: add driver for Ingenic SoC CGU clocks Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-27 23:00   ` James Hogan
2015-04-27 23:00     ` James Hogan
2015-04-28 10:17   ` James Hogan
2015-04-28 10:17     ` James Hogan
2015-05-20 23:16   ` Stephen Boyd
2015-04-24 13:17 ` [PATCH v4 26/37] MIPS,clk: migrate JZ4740 to common clock framework Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-05-13  2:52   ` Michael Turquette
2015-05-13  2:52     ` Michael Turquette
2015-05-24 15:01     ` Paul Burton
2015-05-24 15:01       ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 27/37] MIPS,clk: move jz4740_clock_set_wait_mode to jz4740-cgu Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-05-13  2:56   ` [PATCH v4 27/37] MIPS, clk: " Michael Turquette
2015-05-13  2:56     ` Michael Turquette
2015-04-24 13:17 ` [PATCH v4 28/37] MIPS,clk: move jz4740 UDC auto suspend functions " Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-05-13  3:06   ` [PATCH v4 28/37] MIPS, clk: " Michael Turquette
2015-05-13  3:06     ` Michael Turquette
2015-05-24 15:02     ` Paul Burton
2015-05-24 15:02       ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 29/37] MIPS,clk: move jz4740 clock suspend,resume " Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 30/37] clk: ingenic: add JZ4780 CGU support Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-05-20 23:07   ` Stephen Boyd
2015-04-24 13:17 ` [PATCH v4 31/37] MIPS: JZ4740: remove clock.h Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 32/37] MIPS: JZ4740: only detect RAM size if not specified in DT Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 33/37] devicetree: document Ingenic SoC UART binding Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 34/37] serial: 8250_ingenic: support for Ingenic SoC UARTs Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 35/37] MIPS: JZ4740: use Ingenic SoC UART driver Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-24 13:17 ` [PATCH v4 36/37] MIPS: ingenic: initial JZ4780 support Paul Burton
2015-04-24 13:17   ` Paul Burton
2015-04-28 10:36   ` James Hogan
2015-04-28 10:36     ` James Hogan
2015-04-24 13:17 ` [PATCH v4 37/37] MIPS: ingenic: initial MIPS Creator CI20 support Paul Burton
2015-04-24 13:17   ` Paul Burton

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=553F64EC.8040602@imgtec.com \
    --to=james.hogan@imgtec.com \
    --cc=jason@lakedaemon.net \
    --cc=lars@metafoo.de \
    --cc=linux-mips@linux-mips.org \
    --cc=paul.burton@imgtec.com \
    --cc=ralf@linux-mips.org \
    --cc=tglx@linutronix.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox