Re: [PATCH v2] MIPS: SMP-CPS: Fix address for GCR_ACCESS register for CM3 and later

[Thomas Bogendoerfer <tsbogend@alpha.franken.de>]

On Mon, Jul 22, 2024 at 03:15:39PM +0200, Gregory CLEMENT wrote:
> When the CM block migrated from CM2.5 to CM3.0, the address offset for
> the Global CSR Access Privilege register was modified. We saw this in
> the "MIPS64 I6500 Multiprocessing System Programmer's Guide," it is
> stated that "the Global CSR Access Privilege register is located at
> offset 0x0120" in section 5.4. It is at least the same for I6400.
> 
> This fix allows to use the VP cores in SMP mode if the reset values
> were modified by the bootloader.
> 
> Based on the work of Vladimir Kondratiev
> <vladimir.kondratiev@mobileye.com> and the feedback from Jiaxun Yang
> <jiaxun.yang@flygoat.com>.
> 
> Fixes: 197e89e0984a ("MIPS: mips-cm: Implement mips_cm_revision")
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> Changes in v2:
> - Based the detection on the CM version and not on a single CPU version
> - Renamed the macro accordingly
> - Link to v1: https://lore.kernel.org/r/20240719-smp_i6500-v1-1-8738e67d4802@bootlin.com
> ---
>  arch/mips/include/asm/mips-cm.h | 4 ++++
>  arch/mips/kernel/smp-cps.c      | 5 ++++-
>  2 files changed, 8 insertions(+), 1 deletion(-)

applied to mips-next.

Thomas.

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