Re: [PATCH v2] MIPS: SMP-CPS: Fix address for GCR_ACCESS register for CM3 and later

["Jiaxun Yang" <jiaxun.yang@flygoat.com>]

在2024年7月22日七月 下午9:15，Gregory CLEMENT写道：
> When the CM block migrated from CM2.5 to CM3.0, the address offset for
> the Global CSR Access Privilege register was modified. We saw this in
> the "MIPS64 I6500 Multiprocessing System Programmer's Guide," it is
> stated that "the Global CSR Access Privilege register is located at
> offset 0x0120" in section 5.4. It is at least the same for I6400.
>
> This fix allows to use the VP cores in SMP mode if the reset values
> were modified by the bootloader.
>
> Based on the work of Vladimir Kondratiev
> <vladimir.kondratiev@mobileye.com> and the feedback from Jiaxun Yang
> <jiaxun.yang@flygoat.com>.
>
> Fixes: 197e89e0984a ("MIPS: mips-cm: Implement mips_cm_revision")
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>

Thanks for getting it corrected!
This patch is ideal for fixes tree.

Thanks
- Jiaxun

> ---
> Changes in v2:
> - Based the detection on the CM version and not on a single CPU version
> - Renamed the macro accordingly
> - Link to v1: 
> https://lore.kernel.org/r/20240719-smp_i6500-v1-1-8738e67d4802@bootlin.com
> ---
>  arch/mips/include/asm/mips-cm.h | 4 ++++
>  arch/mips/kernel/smp-cps.c      | 5 ++++-
>  2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
> index 3d9efc802e36..10e96b119c36 100644
> --- a/arch/mips/include/asm/mips-cm.h
> +++ b/arch/mips/include/asm/mips-cm.h
> @@ -240,6 +240,10 @@ GCR_ACCESSOR_RO(32, 0x0d0, gic_status)
>  GCR_ACCESSOR_RO(32, 0x0f0, cpc_status)
>  #define CM_GCR_CPC_STATUS_EX			BIT(0)
> 
> +/* GCR_ACCESS - Controls core/IOCU access to GCRs */
> +GCR_ACCESSOR_RW(32, 0x120, access_cm3)
> +#define CM_GCR_ACCESS_ACCESSEN			GENMASK(7, 0)
> +
>  /* GCR_L2_CONFIG - Indicates L2 cache configuration when Config5.L2C=1 
> */
>  GCR_ACCESSOR_RW(32, 0x130, l2_config)
>  #define CM_GCR_L2_CONFIG_BYPASS			BIT(20)
> diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
> index e074138ffd7f..05174aa9881c 100644
> --- a/arch/mips/kernel/smp-cps.c
> +++ b/arch/mips/kernel/smp-cps.c
> @@ -325,7 +325,10 @@ static void boot_core(unsigned int core, unsigned 
> int vpe_id)
>  	write_gcr_co_reset_ext_base(CM_GCR_Cx_RESET_EXT_BASE_UEB);
> 
>  	/* Ensure the core can access the GCRs */
> -	set_gcr_access(1 << core);
> +	if (mips_cm_revision() < CM_REV_CM3)
> +		set_gcr_access(1 << core);
> +	else
> +		set_gcr_access_cm3(1 << core);
> 
>  	if (mips_cpc_present()) {
>  		/* Reset the core */
>
> ---
> base-commit: 9298d51eb3af24f88b211087eb698399f9efa439
> change-id: 20240719-smp_i6500-8cb233878c41
>
> Best regards,
> -- 
> Gregory CLEMENT <gregory.clement@bootlin.com>

-- 
- Jiaxun