From: "Jiaxun Yang" <jiaxun.yang@flygoat.com>
To: "Maciej W. Rozycki" <macro@orcam.me.uk>
Cc: "Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
linux-kernel@vger.kernel.org,
"stable@vger.kernel.org" <stable@vger.kernel.org>
Subject: Re: [PATCH fixes 3/4] MIPS: cps-vec: Replace MT instructions with macros
Date: Fri, 28 Jun 2024 01:36:12 +0100 [thread overview]
Message-ID: <bf198418-ecb4-4880-8eed-f0af77d18e1a@app.fastmail.com> (raw)
In-Reply-To: <alpine.DEB.2.21.2406272046020.43454@angie.orcam.me.uk>
在2024年6月27日六月 下午8:51,Maciej W. Rozycki写道:
> On Thu, 27 Jun 2024, Jiaxun Yang wrote:
>
>> > how about simply enforcing the need for a correct toolchain instead
>> > of making the code ugly ?
>>
>> Unfortunately, MT for microMIPS which I'm trying to bring up is only in
>> binutils master, it's not in any binutils release yet.
>
> It's not yet in binutils master either. Has there been any actual chip
> taped out with this instruction subset supported?
interAptiv derivative (with MIPS R5 and microMIPS) from CIP which is not GA yet.
Thanks
>
> Maciej
--
- Jiaxun
next prev parent reply other threads:[~2024-06-28 0:36 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-16 13:25 [PATCH fixes 0/4] MIPS: MT ASE fixes Jiaxun Yang
2024-06-16 13:25 ` [PATCH fixes 1/4] MIPS: mipsmtregs: Fix target register for MFTC0 Jiaxun Yang
2024-06-19 11:32 ` Jiaxun Yang
2024-06-19 11:37 ` Jiaxun Yang
2024-06-20 14:43 ` Thomas Bogendoerfer
2024-06-21 8:25 ` Thomas Bogendoerfer
2024-06-16 13:25 ` [PATCH fixes 2/4] MIPS: asmmacro: Fix MT ASE macros Jiaxun Yang
2024-06-16 13:25 ` [PATCH fixes 3/4] MIPS: cps-vec: Replace MT instructions with macros Jiaxun Yang
2024-06-27 9:00 ` Thomas Bogendoerfer
2024-06-27 11:14 ` Jiaxun Yang
2024-06-27 19:51 ` Maciej W. Rozycki
2024-06-28 0:36 ` Jiaxun Yang [this message]
2024-06-16 13:25 ` [PATCH fixes 4/4] MIPS: Use toolchain MT ASE support whenever possible Jiaxun Yang
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