* Re: [PATCH] JAZZ: disable PIT; cleanup R4030 clockevent
From: Ralf Baechle @ 2007-11-01 15:07 UTC (permalink / raw)
To: Thomas Bogendoerfer; +Cc: linux-mips
In-Reply-To: <20071101125236.GA16577@alpha.franken.de>
On Thu, Nov 01, 2007 at 01:52:36PM +0100, Thomas Bogendoerfer wrote:
> PIT doesn't work, disable it completly
I think this is the explanation:
include/asm-mips/mach-jazz/timex.h:#define CLOCK_TICK_RATE 100
while the PIT code actually expects 1193182.
Turns out that due to a recent Qemu bug which made the probe for the cp0
compare interrupt fail the Malta code did fall back from the compare timer
to the i8253 PIT for the clockevent device. Works perfectly well.
Ralf
^ permalink raw reply
* Re: implementation of software suspend on MIPS. (system log)
From: J. Scott Kasten @ 2007-11-01 15:00 UTC (permalink / raw)
To: Hyon Lim; +Cc: linux-mips
In-Reply-To: <dd7dc2bc0711010737m7d0d1586w894d5500d1d8500b@mail.gmail.com>
On Thu, 1 Nov 2007, Hyon Lim wrote:
> Thank you for comments.
> The remain work of my software suspend on MIPS project is resume procedure.
> I already confirmed that suspend function was work. (See my post which
> contains system log).
>
> In an i386 implementation, there are only few assembly code for suspend and
> resume procedure.
> (You can refer :
> http://lxr.linux.no/source/arch/i386/power/swsusp.S?v=2.6.10)
> So, my work will be similar with i386 implementation. Assembly code used in
> i386 implementation are several processor context related job
> and copy saved page to memory. Instruction used in my MIPS implementation
> will be compatible to most of MIPS processor.
> Because the instruction used in implementation is very basic (store and load
> and branch).
>
> I agree your opinion related to maintainability and readability. So I
> implement my work with C and few assembly code.
> Thank you for advice.
>
I look forward to your eventual success. :)
^ permalink raw reply
* Re: implementation of software suspend on MIPS. (system log)
From: Hyon Lim @ 2007-11-01 14:37 UTC (permalink / raw)
To: J. Scott Kasten; +Cc: linux-mips
In-Reply-To: <Pine.LNX.4.64.0711010908090.11339@pixie.tetracon-eng.net>
[-- Attachment #1: Type: text/plain, Size: 2780 bytes --]
Thank you for comments.
The remain work of my software suspend on MIPS project is resume procedure.
I already confirmed that suspend function was work. (See my post which
contains system log).
In an i386 implementation, there are only few assembly code for suspend and
resume procedure.
(You can refer :
http://lxr.linux.no/source/arch/i386/power/swsusp.S?v=2.6.10)
So, my work will be similar with i386 implementation. Assembly code used in
i386 implementation are several processor context related job
and copy saved page to memory. Instruction used in my MIPS implementation
will be compatible to most of MIPS processor.
Because the instruction used in implementation is very basic (store and load
and branch).
I agree your opinion related to maintainability and readability. So I
implement my work with C and few assembly code.
Thank you for advice.
On 11/1/07, J. Scott Kasten <jscottkasten@yahoo.com> wrote:
>
>
>
> On Thu, 1 Nov 2007, Hyon Lim wrote:
>
> > I think the reason of assembly implementation is processor context
> > replacement.
>
> Understood. Assembly may indeed be required for specific things like
> restoring register state or fiddling with the cache if there aren't
> already macros or functions in the kernel that do exactly what you need.
>
> > The second reason that I thinking is calling convention of C language.
>
> It's not uncommon at all to have assembly language glue, say between a
> BIOS callback and the C language routine that does the work.
>
> In your original post, you mentioned tracking variables and things that
> suggested a module that does much more that just load some odd registers
> or flip around a function call stack. If that is indeed the case, then
> for sake of maintainablility and readability, one would be strongly
> encouraged to write the core stuff in plain old C and sprinkle in assembly
> glue code as required.
>
> Think about it this way. MIPS is a pretty large family of CPUs, each with
> it's own strange behaviors. Several of those people on this list spend a
> lot of time tweeking that assembly to make it work cleanly across various
> CPUs. It's a lot easier to understand 25 lines of assembly interface code
> and 200 lines of C code, than an entire 1000 line module written in
> assembly. It's also a lot easier when you can shove most of the work over
> to the compiler, especially if others like your work and want to
> generalize it for use on many other MIPS CPUs.
>
> I guess the real question here is how complex do you think your code needs
> to be? That should determine your path.
>
> Regards,
>
> -S-
>
--
Hyon Lim (임현)
Mobile. 010-8212-1240 (Intl' Call : +82-10-8212-1240)
Fax. 032-232-0578 (Intl' Available)
Homepage : http://www.alexlab.net
Blog : http://www.alexlab.net/blog
[-- Attachment #2: Type: text/html, Size: 3553 bytes --]
^ permalink raw reply
* Re: MIPS assembly directives in GCC
From: Thiemo Seufer @ 2007-11-01 14:26 UTC (permalink / raw)
To: Hyon Lim; +Cc: linux-mips
In-Reply-To: <dd7dc2bc0711010536l18f9f2f6gbda4e9ef1158da61@mail.gmail.com>
Hyon Lim wrote:
> I investigated kernel assembly source code in my kernel (2.6.10).
> I found that there are a lot of assembly directives (e.g., .align, .set
> reorder, .cpload, .frame etc.).
> Is there any documents which explains those directives? (not only I
> described above. All of directives)
Short of reading the assembler sourcecode I believe the best document
is "See MIPS Run Linux".
Thiemo
^ permalink raw reply
* Re: implementation of software suspend on MIPS. (system log)
From: J. Scott Kasten @ 2007-11-01 13:41 UTC (permalink / raw)
To: Hyon Lim; +Cc: linux-mips
In-Reply-To: <dd7dc2bc0711010211k530296a4u8dc9272673075248@mail.gmail.com>
On Thu, 1 Nov 2007, Hyon Lim wrote:
> I think the reason of assembly implementation is processor context
> replacement.
Understood. Assembly may indeed be required for specific things like
restoring register state or fiddling with the cache if there aren't
already macros or functions in the kernel that do exactly what you need.
> The second reason that I thinking is calling convention of C language.
It's not uncommon at all to have assembly language glue, say between a
BIOS callback and the C language routine that does the work.
In your original post, you mentioned tracking variables and things that
suggested a module that does much more that just load some odd registers
or flip around a function call stack. If that is indeed the case, then
for sake of maintainablility and readability, one would be strongly
encouraged to write the core stuff in plain old C and sprinkle in assembly
glue code as required.
Think about it this way. MIPS is a pretty large family of CPUs, each with
it's own strange behaviors. Several of those people on this list spend a
lot of time tweeking that assembly to make it work cleanly across various
CPUs. It's a lot easier to understand 25 lines of assembly interface code
and 200 lines of C code, than an entire 1000 line module written in
assembly. It's also a lot easier when you can shove most of the work over
to the compiler, especially if others like your work and want to
generalize it for use on many other MIPS CPUs.
I guess the real question here is how complex do you think your code needs
to be? That should determine your path.
Regards,
-S-
^ permalink raw reply
* Re: [PATCH][MIPS] fix Cobalt IRQ comment
From: Ralf Baechle @ 2007-11-01 13:13 UTC (permalink / raw)
To: Yoichi Yuasa; +Cc: linux-mips
In-Reply-To: <20071101215123.5e65eee6.yoichi_yuasa@tripeaks.co.jp>
On Thu, Nov 01, 2007 at 09:51:23PM +0900, Yoichi Yuasa wrote:
> Fixed Cobalt IRQ comment.
> Cobalt kernel uses CP0 counter now.
Thanks, applied.
Ralf
^ permalink raw reply
* Re: [PATCH][MIPS] clean up au1xxx_irqmap.c include files
From: Ralf Baechle @ 2007-11-01 13:12 UTC (permalink / raw)
To: Yoichi Yuasa; +Cc: linux-mips
In-Reply-To: <20071101213539.9c47c3e9.yoichi_yuasa@tripeaks.co.jp>
On Thu, Nov 01, 2007 at 09:35:39PM +0900, Yoichi Yuasa wrote:
> Clean up au1xxx_irqmap.c include files.
Thanks, queued up for 2.6.25.
Ralf
^ permalink raw reply
* Re: [PATCH][MIPS] bcm47xx: remove unneeded clear_c0_status()
From: Ralf Baechle @ 2007-11-01 13:03 UTC (permalink / raw)
To: Yoichi Yuasa; +Cc: linux-mips
In-Reply-To: <20071101213036.c383957f.yoichi_yuasa@tripeaks.co.jp>
On Thu, Nov 01, 2007 at 09:30:36PM +0900, Yoichi Yuasa wrote:
> Remove unneeded clear_c0_status().
> irq_cpu routines take care of it.
Actually this write is plain nonsense; it has no effect. The only time
acknowledging an interrupt in c0_cause is needed is for the two software
interrupts but the only user of these is SMTC.
Ralf
^ permalink raw reply
* [PATCH][MIPS] fix Cobalt IRQ comment
From: Yoichi Yuasa @ 2007-11-01 12:51 UTC (permalink / raw)
To: Ralf Baechle; +Cc: yoichi_yuasa, linux-mips
Fixed Cobalt IRQ comment.
Cobalt kernel uses CP0 counter now.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
diff -pruN -X mips/Documentation/dontdiff mips-orig/include/asm-mips/mach-cobalt/irq.h mips/include/asm-mips/mach-cobalt/irq.h
--- mips-orig/include/asm-mips/mach-cobalt/irq.h 2007-10-27 17:13:58.239256750 +0900
+++ mips/include/asm-mips/mach-cobalt/irq.h 2007-10-27 17:17:45.905485000 +0900
@@ -35,7 +35,7 @@
* 4 - ethernet
* 5 - 16550 UART
* 6 - cascade i8259
- * 7 - CP0 counter (unused)
+ * 7 - CP0 counter
*/
#define MIPS_CPU_IRQ_BASE 16
@@ -48,7 +48,6 @@
#define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
#define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
-
#define GT641XX_IRQ_BASE 24
#include <asm/irq_gt641xx.h>
^ permalink raw reply
* [PATCH] JAZZ: disable PIT; cleanup R4030 clockevent
From: Thomas Bogendoerfer @ 2007-11-01 12:52 UTC (permalink / raw)
To: linux-mips; +Cc: ralf
PIT doesn't work, disable it completly
make r4030 clockevent code look like other mips clockevent code
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 97da953..c4f7e60 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -119,7 +119,6 @@ config MACH_JAZZ
select CEVT_R4K
select GENERIC_ISA_DMA
select IRQ_CPU
- select I8253
select I8259
select ISA
select PCSPEAKER
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 1dac9e1..a629719 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -118,16 +118,16 @@ static void r4030_set_mode(enum clock_event_mode mode,
struct clock_event_device r4030_clockevent = {
.name = "r4030",
.features = CLOCK_EVT_FEAT_PERIODIC,
- .rating = 100,
+ .rating = 300,
.irq = JAZZ_TIMER_IRQ,
- .cpumask = CPU_MASK_CPU0,
.set_mode = r4030_set_mode,
};
static irqreturn_t r4030_timer_interrupt(int irq, void *dev_id)
{
- r4030_clockevent.event_handler(&r4030_clockevent);
+ struct clock_event_device *cd = dev_id;
+ cd->event_handler(cd);
return IRQ_HANDLED;
}
@@ -135,15 +135,22 @@ static struct irqaction r4030_timer_irqaction = {
.handler = r4030_timer_interrupt,
.flags = IRQF_DISABLED,
.mask = CPU_MASK_CPU0,
- .name = "timer",
+ .name = "R4030 timer",
};
void __init plat_time_init(void)
{
- struct irqaction *irq = &r4030_timer_irqaction;
+ struct clock_event_device *cd = &r4030_clockevent;
+ struct irqaction *action = &r4030_timer_irqaction;
+ unsigned int cpu = smp_processor_id();
BUG_ON(HZ != 100);
+ cd->cpumask = cpumask_of_cpu(cpu);
+ clockevents_register_device(cd);
+ action->dev_id = cd;
+ setup_irq(JAZZ_TIMER_IRQ, action);
+
/*
* Set clock to 100Hz.
*
@@ -151,8 +158,4 @@ void __init plat_time_init(void)
* a programmable 4-bit divider. This makes it fairly inflexible.
*/
r4030_write_reg32(JAZZ_TIMER_INTERVAL, 9);
- setup_irq(JAZZ_TIMER_IRQ, irq);
-
- clockevents_register_device(&r4030_clockevent);
- setup_pit_timer();
}
--
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply related
* MIPS assembly directives in GCC
From: Hyon Lim @ 2007-11-01 12:36 UTC (permalink / raw)
To: linux-mips
[-- Attachment #1: Type: text/plain, Size: 454 bytes --]
I investigated kernel assembly source code in my kernel (2.6.10).
I found that there are a lot of assembly directives (e.g., .align, .set
reorder, .cpload, .frame etc.).
Is there any documents which explains those directives? (not only I
described above. All of directives)
--
Hyon Lim (임현)
Mobile. 010-8212-1240 (Intl' Call : +82-10-8212-1240)
Fax. 032-232-0578 (Intl' Available)
Homepage : http://www.alexlab.net
Blog : http://www.alexlab.net/blog
[-- Attachment #2: Type: text/html, Size: 609 bytes --]
^ permalink raw reply
* [PATCH][MIPS] clean up au1xxx_irqmap.c include files
From: Yoichi Yuasa @ 2007-11-01 12:35 UTC (permalink / raw)
To: Ralf Baechle; +Cc: yoichi_yuasa, linux-mips
Clean up au1xxx_irqmap.c include files.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/au1000/common/au1xxx_irqmap.c mips/arch/mips/au1000/common/au1xxx_irqmap.c
--- mips-orig/arch/mips/au1000/common/au1xxx_irqmap.c 2007-10-26 23:35:58.350582750 +0900
+++ mips/arch/mips/au1000/common/au1xxx_irqmap.c 2007-10-26 23:54:59.221882750 +0900
@@ -25,27 +25,10 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
-#include <linux/errno.h>
#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/kernel_stat.h>
-#include <linux/module.h>
-#include <linux/signal.h>
-#include <linux/sched.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/timex.h>
-#include <linux/slab.h>
-#include <linux/random.h>
-#include <linux/delay.h>
-#include <linux/bitops.h>
-
-#include <asm/bootinfo.h>
-#include <asm/io.h>
-#include <asm/mipsregs.h>
-#include <asm/system.h>
-#include <asm/mach-au1x00/au1000.h>
+#include <linux/kernel.h>
+
+#include <au1000.h>
/* The IC0 interrupt table. This is processor, rather than
* board dependent, so no reason to keep this info in the board
^ permalink raw reply
* [PATCH][MIPS] bcm47xx: remove unneeded clear_c0_status()
From: Yoichi Yuasa @ 2007-11-01 12:30 UTC (permalink / raw)
To: Ralf Baechle; +Cc: yoichi_yuasa, linux-mips
Remove unneeded clear_c0_status().
irq_cpu routines take care of it.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
diff -pruN -X mips/Documentation/dontdiff mips-orig/arch/mips/bcm47xx/irq.c mips/arch/mips/bcm47xx/irq.c
--- mips-orig/arch/mips/bcm47xx/irq.c 2007-10-26 23:35:58.630600250 +0900
+++ mips/arch/mips/bcm47xx/irq.c 2007-10-26 23:40:22.587096500 +0900
@@ -33,8 +33,6 @@ void plat_irq_dispatch(void)
cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
- clear_c0_status(cause);
-
if (cause & CAUSEF_IP7)
do_IRQ(7);
if (cause & CAUSEF_IP2)
^ permalink raw reply
* [PATCH] SNI: register a02r clockevent; don't use PIT timer
From: Thomas Bogendoerfer @ 2007-11-01 10:36 UTC (permalink / raw)
To: linux-mips; +Cc: ralf
Register A20R clockevent
Remove PIT timer setup because it doesn't work
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---
diff --git a/arch/mips/sni/time.c b/arch/mips/sni/time.c
index 60bc62e..6f339af 100644
--- a/arch/mips/sni/time.c
+++ b/arch/mips/sni/time.c
@@ -1,6 +1,7 @@
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/time.h>
+#include <linux/clockchips.h>
#include <asm/i8253.h>
#include <asm/sni.h>
@@ -80,7 +81,7 @@ static void __init sni_a20r_timer_setup(void)
unsigned int cpu = smp_processor_id();
cd->cpumask = cpumask_of_cpu(cpu);
-
+ clockevents_register_device(cd);
action->dev_id = cd;
setup_irq(SNI_A20R_IRQ_TIMER, &a20r_irqaction);
}
@@ -169,8 +170,6 @@ void __init plat_time_init(void)
mips_hpt_frequency = r4k_tick * HZ;
- setup_pit_timer();
-
switch (sni_brd_type) {
case SNI_BRD_10:
case SNI_BRD_10NEW:
--
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea. [ RFC1925, 2.3 ]
^ permalink raw reply related
* Re: implementation of software suspend on MIPS. (system log)
From: Hyon Lim @ 2007-11-01 9:11 UTC (permalink / raw)
To: J. Scott Kasten; +Cc: linux-mips
In-Reply-To: <Pine.SGI.4.60.0710312221360.4697@zeus.tetracon-eng.net>
[-- Attachment #1: Type: text/plain, Size: 1387 bytes --]
I think the reason of assembly implementation is processor context
replacement.
Processor context should be replaced when suspend or resume process.
So I think that code should be implemented using assembly language.
The second reason that I thinking is calling convention of C language.
How do you think?
On 11/1/07, J. Scott Kasten <jscottkasten@yahoo.com> wrote:
>
>
> On Thu, 1 Nov 2007, Hyon Lim wrote:
>
> > Yes. you're right. I did same as you said.
> > However, is there any options for disassembly with variable name?
> > Often I cannot find that variable's allocated register.
> > There is only r0,r1... but I want a comment for variable assignment
> > status.
>
> I just have to ask the question, but is it really necessary to code the
> whole thing in assembly? I understand that the interface probably does
> need to be, but the main body of the function? If it's very large or
> complicated, it would seem simpler to use C and write assembly glue to
> pull it all together rather than trying to debug hand assembly. Many of
> us here have spent hours before tracking down problems with stale data in
> branch delay slots. The compiler is a tad more convienient.
>
> Regards,
>
> -S-
>
>
--
Hyon Lim (임현)
Mobile. 010-8212-1240 (Intl' Call : +82-10-8212-1240)
Fax. 032-232-0578 (Intl' Available)
Homepage : http://www.alexlab.net
Blog : http://www.alexlab.net/blog
[-- Attachment #2: Type: text/html, Size: 1929 bytes --]
^ permalink raw reply
* Re: implementation of software suspend on MIPS. (system log)
From: J. Scott Kasten @ 2007-11-01 2:27 UTC (permalink / raw)
To: Hyon Lim; +Cc: linux-mips
In-Reply-To: <dd7dc2bc0710311846ve03e03eued4ed72c89b06e4f@mail.gmail.com>
On Thu, 1 Nov 2007, Hyon Lim wrote:
> Yes. you're right. I did same as you said.
> However, is there any options for disassembly with variable name?
> Often I cannot find that variable's allocated register.
> There is only r0,r1... but I want a comment for variable assignment
> status.
I just have to ask the question, but is it really necessary to code the
whole thing in assembly? I understand that the interface probably does
need to be, but the main body of the function? If it's very large or
complicated, it would seem simpler to use C and write assembly glue to
pull it all together rather than trying to debug hand assembly. Many of
us here have spent hours before tracking down problems with stale data in
branch delay slots. The compiler is a tad more convienient.
Regards,
-S-
^ permalink raw reply
* Re: implementation of software suspend on MIPS. (system log)
From: Hyon Lim @ 2007-11-01 1:46 UTC (permalink / raw)
To: Andrew Dyer; +Cc: linux-mips
In-Reply-To: <DDAE9570F73FC744918E843E20BE598B096E8E@server1.RightHand.righthandtech.com>
[-- Attachment #1: Type: text/plain, Size: 1021 bytes --]
Yes. you're right. I did same as you said.
However, is there any options for disassembly with variable name?
Often I cannot find that variable's allocated register.
There is only r0,r1... but I want a comment for variable assignment status.
On 11/1/07, Andrew Dyer <adyer@righthandtech.com> wrote:
>
> > The code of resume process should be implemented on
> arch/xxx/power/swsusp.S
> > So it should be implemented by assembly.
> > That's the problem...
> > I've no idea about complex assembly programming. :-)
> > Could you recommend any pdf or website?
>
> Whenever I have to do something moderately complex in assy. language, I
> often find it helpful to code the thing in C and run it through the compiler
> and look at the generated assy. language. Oftentimes you can modify the
> output of the compiler without too much trouble.
>
>
--
Hyon Lim (임현)
Mobile. 010-8212-1240 (Intl' Call : +82-10-8212-1240)
Fax. 032-232-0578 (Intl' Available)
Homepage : http://www.alexlab.net
Blog : http://www.alexlab.net/blog
[-- Attachment #2: Type: text/html, Size: 1505 bytes --]
^ permalink raw reply
* [PATCH] Put cast inside macro instead of all the callers
From: Andrew Sharp @ 2007-10-31 21:11 UTC (permalink / raw)
To: linux-mips; +Cc: Ralf Baechle
Resend: I tried sending this a couple of days ago but haven't seen it.
Wondering if it got stuck in a spam filter or our lovely exchange
server or something.
Since all the callers of the PHYS_TO_XKPHYS macro call with a constant,
put the cast to LL inside the macro where it really should be rather
than in all the callers. This makes macros like PHYS_TO_XKSEG_UNCACHED
work without gcc whining.
Hopefully this will apply ok.
Signed-off-by: Andrew Sharp <andy.sharp@onstor.com>
---
arch/mips/lib/uncached.c | 12 ++++++------
include/asm-mips/addrspace.h | 2 +-
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/mips/lib/uncached.c b/arch/mips/lib/uncached.c
index 2388f7f..bbca1ea 100644
--- a/arch/mips/lib/uncached.c
+++ b/arch/mips/lib/uncached.c
@@ -45,9 +45,9 @@ unsigned long __init run_uncached(void *func)
if (sp >= (long)CKSEG0 && sp < (long)CKSEG2)
usp = CKSEG1ADDR(sp);
#ifdef CONFIG_64BIT
- else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0LL, 0) &&
- (long long)sp < (long long)PHYS_TO_XKPHYS(8LL, 0))
- usp = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED,
+ else if ((long long)sp >= (long long)PHYS_TO_XKPHYS(0, 0) &&
+ (long long)sp < (long long)PHYS_TO_XKPHYS(8, 0))
+ usp = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
XKPHYS_TO_PHYS((long long)sp));
#endif
else {
@@ -57,9 +57,9 @@ unsigned long __init run_uncached(void *func)
if (lfunc >= (long)CKSEG0 && lfunc < (long)CKSEG2)
ufunc = CKSEG1ADDR(lfunc);
#ifdef CONFIG_64BIT
- else if ((long long)lfunc >= (long long)PHYS_TO_XKPHYS(0LL, 0) &&
- (long long)lfunc < (long long)PHYS_TO_XKPHYS(8LL, 0))
- ufunc = PHYS_TO_XKPHYS((long long)K_CALG_UNCACHED,
+ else if ((long long)lfunc >= (long long)PHYS_TO_XKPHYS(0, 0) &&
+ (long long)lfunc < (long long)PHYS_TO_XKPHYS(8, 0))
+ ufunc = PHYS_TO_XKPHYS(K_CALG_UNCACHED,
XKPHYS_TO_PHYS((long long)lfunc));
#endif
else {
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 964c5ed..1bc23e8 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -127,7 +127,7 @@
#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
#define PHYS_TO_XKPHYS(cm,a) (_CONST64_(0x8000000000000000) | \
- ((cm)<<59) | (a))
+ (_CONST64_(cm)<<59) | (a))
#if defined (CONFIG_CPU_R4300) \
|| defined (CONFIG_CPU_R4X00) \
--
1.4.4.4
^ permalink raw reply related
* RE: implementation of software suspend on MIPS. (system log)
From: Uhler, Mike @ 2007-10-31 18:32 UTC (permalink / raw)
To: Hyon Lim, Ralf Baechle; +Cc: linux-mips
In-Reply-To: <dd7dc2bc0710311115x51dfab0bt97cdd810d21d120c@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2720 bytes --]
There are various sources of information available on MIPS assembly language programming. The easiest way to get what you want is to write the code in C, then push it through the compiler to see what instructions it generates. You can then hack that code to work in your context.
Beyond that, Ralf mentioned the book "See MIPS Run Linux", by Dominic Sweetman. There is also the GNU gas manual and the MIPS SDE Programmer's Guide (see http://www.mips.com/products/resource-library/product-materials/software) or other references on MIPS assembly language programming.
/gmu
---
Michael Uhler, VP Architecture, Software and Platform Engineering
MIPS Technologies, Inc. Email: uhler AT mips.com
1225 Charleston Road Voice: (650)567-5025
Mountain View, CA 94043
________________________________
From: linux-mips-bounce@linux-mips.org [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Hyon Lim
Sent: Wednesday, October 31, 2007 11:15 AM
To: Ralf Baechle
Cc: linux-mips@linux-mips.org
Subject: Re: implementation of software suspend on MIPS. (system log)
The problem is resume process.
Some page copy and other remaining process wasn't implemented.
The code of resume process should be implemented on arch/xxx/power/swsusp.S
So it should be implemented by assembly.
That's the problem...
I've no idea about complex assembly programming. :-)
Could you recommend any pdf or website?
On 10/31/07, Ralf Baechle <ralf@linux-mips.org> wrote:
On Wed, Oct 31, 2007 at 04:15:57AM +0900, Hyon Lim wrote:
> [DEBUG] Swsusp_write() @ kernel/power/swsusp.c,874
> [DEBUG] write_suspend_image(), kernel/power/swsusp.c,407
> [DEBUG] init_header(), kernel/power/swsusp.c,337
> [DEBUG] dump_info(), kernel/power/swsusp.c,321
> swsusp: Version: 132618
> swsusp: Num Pages: 8192
> swsusp: UTS Sys: Linux
> swsusp: UTS Node: (none)
> swsusp: UTS Release: 2.6.10_SELP_MIPS
> swsusp: UTS Version: #95 Wed Oct 30 03:46:35 KST 2007
> swsusp: UTS Machine: mips
> swsusp: UTS Domain: (none)
> swsusp: CPUs: 1
> swsusp: Image: 1896 Pages
> swsusp: Pagedir: 0 Pages
> [DEBUG] data_write(), kernel/power/swsusp.c,303
> Writing data to swap (1896 pages)... done
> Writing pagedir (8 pages)
> S|
> Powering off system
> Cold reset
>
> This is system log of my implementation.
Excellent, this is looking promising.
Do you still need any help?
Ralf
--
Hyon Lim (임현)
Mobile. 010-8212-1240 (Intl' Call : +82-10-8212-1240)
Fax. 032-232-0578 (Intl' Available)
Homepage : http://www.alexlab.net
Blog : http://www.alexlab.net/blog
[-- Attachment #2: Type: text/html, Size: 4710 bytes --]
^ permalink raw reply
* RE: implementation of software suspend on MIPS. (system log)
From: Uhler, Mike @ 2007-10-31 18:32 UTC (permalink / raw)
To: Hyon Lim, Ralf Baechle; +Cc: linux-mips
In-Reply-To: <dd7dc2bc0710311115x51dfab0bt97cdd810d21d120c@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 2720 bytes --]
There are various sources of information available on MIPS assembly language programming. The easiest way to get what you want is to write the code in C, then push it through the compiler to see what instructions it generates. You can then hack that code to work in your context.
Beyond that, Ralf mentioned the book "See MIPS Run Linux", by Dominic Sweetman. There is also the GNU gas manual and the MIPS SDE Programmer's Guide (see http://www.mips.com/products/resource-library/product-materials/software) or other references on MIPS assembly language programming.
/gmu
---
Michael Uhler, VP Architecture, Software and Platform Engineering
MIPS Technologies, Inc. Email: uhler AT mips.com
1225 Charleston Road Voice: (650)567-5025
Mountain View, CA 94043
________________________________
From: linux-mips-bounce@linux-mips.org [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Hyon Lim
Sent: Wednesday, October 31, 2007 11:15 AM
To: Ralf Baechle
Cc: linux-mips@linux-mips.org
Subject: Re: implementation of software suspend on MIPS. (system log)
The problem is resume process.
Some page copy and other remaining process wasn't implemented.
The code of resume process should be implemented on arch/xxx/power/swsusp.S
So it should be implemented by assembly.
That's the problem...
I've no idea about complex assembly programming. :-)
Could you recommend any pdf or website?
On 10/31/07, Ralf Baechle <ralf@linux-mips.org> wrote:
On Wed, Oct 31, 2007 at 04:15:57AM +0900, Hyon Lim wrote:
> [DEBUG] Swsusp_write() @ kernel/power/swsusp.c,874
> [DEBUG] write_suspend_image(), kernel/power/swsusp.c,407
> [DEBUG] init_header(), kernel/power/swsusp.c,337
> [DEBUG] dump_info(), kernel/power/swsusp.c,321
> swsusp: Version: 132618
> swsusp: Num Pages: 8192
> swsusp: UTS Sys: Linux
> swsusp: UTS Node: (none)
> swsusp: UTS Release: 2.6.10_SELP_MIPS
> swsusp: UTS Version: #95 Wed Oct 30 03:46:35 KST 2007
> swsusp: UTS Machine: mips
> swsusp: UTS Domain: (none)
> swsusp: CPUs: 1
> swsusp: Image: 1896 Pages
> swsusp: Pagedir: 0 Pages
> [DEBUG] data_write(), kernel/power/swsusp.c,303
> Writing data to swap (1896 pages)... done
> Writing pagedir (8 pages)
> S|
> Powering off system
> Cold reset
>
> This is system log of my implementation.
Excellent, this is looking promising.
Do you still need any help?
Ralf
--
Hyon Lim (임현)
Mobile. 010-8212-1240 (Intl' Call : +82-10-8212-1240)
Fax. 032-232-0578 (Intl' Available)
Homepage : http://www.alexlab.net
Blog : http://www.alexlab.net/blog
[-- Attachment #2: Type: text/html, Size: 4710 bytes --]
^ permalink raw reply
* Re: implementation of software suspend on MIPS. (system log)
From: Ralf Baechle @ 2007-10-31 18:30 UTC (permalink / raw)
To: Hyon Lim; +Cc: linux-mips
In-Reply-To: <dd7dc2bc0710311115x51dfab0bt97cdd810d21d120c@mail.gmail.com>
On Thu, Nov 01, 2007 at 03:15:11AM +0900, Hyon Lim wrote:
> The problem is resume process.
> Some page copy and other remaining process wasn't implemented.
> The code of resume process should be implemented on arch/xxx/power/swsusp.S
> So it should be implemented by assembly.
> That's the problem...
> I've no idea about complex assembly programming. :-)
> Could you recommend any pdf or website?
See MIPS Run (ISBN 0120884216) is _the_ best book on this topic. Maybe
a library near you already has it, it's the de facto standard book on
the topic.
Ralf
^ permalink raw reply
* Re: implementation of software suspend on MIPS. (system log)
From: Hyon Lim @ 2007-10-31 18:15 UTC (permalink / raw)
To: Ralf Baechle; +Cc: linux-mips
In-Reply-To: <20071031132553.GF14187@linux-mips.org>
[-- Attachment #1: Type: text/plain, Size: 1519 bytes --]
The problem is resume process.
Some page copy and other remaining process wasn't implemented.
The code of resume process should be implemented on arch/xxx/power/swsusp.S
So it should be implemented by assembly.
That's the problem...
I've no idea about complex assembly programming. :-)
Could you recommend any pdf or website?
On 10/31/07, Ralf Baechle <ralf@linux-mips.org> wrote:
>
> On Wed, Oct 31, 2007 at 04:15:57AM +0900, Hyon Lim wrote:
>
> > [DEBUG] Swsusp_write() @ kernel/power/swsusp.c,874
> > [DEBUG] write_suspend_image(), kernel/power/swsusp.c,407
> > [DEBUG] init_header(), kernel/power/swsusp.c,337
> > [DEBUG] dump_info(), kernel/power/swsusp.c,321
> > swsusp: Version: 132618
> > swsusp: Num Pages: 8192
> > swsusp: UTS Sys: Linux
> > swsusp: UTS Node: (none)
> > swsusp: UTS Release: 2.6.10_SELP_MIPS
> > swsusp: UTS Version: #95 Wed Oct 30 03:46:35 KST 2007
> > swsusp: UTS Machine: mips
> > swsusp: UTS Domain: (none)
> > swsusp: CPUs: 1
> > swsusp: Image: 1896 Pages
> > swsusp: Pagedir: 0 Pages
> > [DEBUG] data_write(), kernel/power/swsusp.c,303
> > Writing data to swap (1896 pages)... done
> > Writing pagedir (8 pages)
> > S|
> > Powering off system
> > Cold reset
> >
> > This is system log of my implementation.
>
> Excellent, this is looking promising.
>
> Do you still need any help?
>
> Ralf
>
--
Hyon Lim (임현)
Mobile. 010-8212-1240 (Intl' Call : +82-10-8212-1240)
Fax. 032-232-0578 (Intl' Available)
Homepage : http://www.alexlab.net
Blog : http://www.alexlab.net/blog
[-- Attachment #2: Type: text/html, Size: 2207 bytes --]
^ permalink raw reply
* Re: implementation of software suspend on MIPS.
From: Ralf Baechle @ 2007-10-31 17:58 UTC (permalink / raw)
To: Hyon Lim; +Cc: linux-mips
In-Reply-To: <dd7dc2bc0710301212s7b364392n39a149764a4117cf@mail.gmail.com>
On Wed, Oct 31, 2007 at 04:12:36AM +0900, Hyon Lim wrote:
> Hello. I need a help for my implementation work on MIPS software suspend.
> From 3month ago, I've been coding software suspend(swsusp) on MIPS arch.
> I'm developing with MIPS32 4KEc embedded processor for digital appliance.
>
> Swsusp has two procedure. the one is suspending procedure and other one is
> resume procedure.
> Yesterday, I confirmed suspending procedure working.
> This is a porting guide of swsusp (
> http://tree.celinuxforum.org/CelfPubWiki/SwSuspendPortingNotes)
> I refered this article.
The article is a bit dated and lacking alot of details.
> The problem I faced is assembly language for MIPS.
> Of course, there are many manuals for this work but, I need a help from MIPS
> expert.
>
> This pseudo code should be implemented by MIPS asm.
>
> for (j = nr_copy_pages; j>0; j--) {
> src = pagedir_nosave[j].src;
> dst = pagedir_nosave[j].dst;
> for (i=0;i<1024;i++) {
> *dst++ = *src++;
> }
> }
>
> nr_copy_pages is unsigned long variable.
The page is refering to some old code which no longer seems to exist in
this form. The array pagedir_nosave has now become a chained list. I
attach a patch for illustration purposes. It illustrates how things work
on recent kernels; I didn't have a 2.6.10 kernel at hand.
If you have further questions on MIPS assembler then I suggest you get a
copy of Dominik Sweetman's excellent "See MIPS Run Linux" book.
> and pagedir_nosave is a
> suspend_pagedir_t<http://lxr.linux.no/source/kernel/power/ident?v=2.6.10;i=suspend_pagedir_t>type
> structure array(pointer). (you can refer following url. Line 101. :
> http://lxr.linux.no/source/kernel/power/swsusp.c?v=2.6.10)
> code skeleton or useful material will be welcomed. (whatever you have.)
>
> The second problem is
> " which register should be prevented? "
>
> I saved $v0-v1. $a0-$a3. $t0-t7. $s0-s7. $t8-t9. $gp,sp,fp,ra.
That sounds about right but I'd need to dive deeper into swsusp to give
you a definitive answer.
Cheers,
Ralf
[MIPS] Skeleton swsusp implementation.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 3196509..38adf9e 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -75,6 +75,8 @@ obj-$(CONFIG_PCSPEAKER) += pcspeaker.o
obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
+obj-$(CONFIG_HIBERNATION) += swsusp.o suspend.o
+
CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index ca13629..f3038dc 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -13,6 +13,7 @@
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
+#include <linux/suspend.h>
#include <asm/ptrace.h>
#include <asm/processor.h>
@@ -337,3 +338,13 @@ void output_irq_cpustat_t_defines(void)
size("#define IC_IRQ_CPUSTAT_T ", irq_cpustat_t);
linefeed;
}
+
+void output_pbe_defines(void)
+{
+ text("/* Linux struct pbe offsets. */");
+ offset("#define PBE_ADDRESS ", struct pbe, address);
+ offset("#define PBE_ORIG_ADDRESS ", struct pbe, orig_address);
+ offset("#define PBE_NEXT ", struct pbe, next);
+ size("#define PBE_SIZE ", struct pbe);
+ linefeed;
+}
diff --git a/arch/mips/kernel/suspend.S b/arch/mips/kernel/suspend.S
new file mode 100644
index 0000000..32b3ec0
--- /dev/null
+++ b/arch/mips/kernel/suspend.S
@@ -0,0 +1,20 @@
+#include <asm/asm-offsets.h>
+#include <asm/regdef.h>
+#include <asm/asm.h>
+
+LEAF(swsusp_arch_suspend)
+ END(swsusp_arch_suspend)
+
+LEAF(swsusp_arch_resume)
+ PTR_LA t0, restore_pblist
+0: PTR_L t1, PBE_ADDRESS(t1)
+ PTR_L t2, PBE_ORIG_ADDRESS(t1)
+ PTR_ADDIU t3, t1, _PAGE_SIZE
+1: REG_L t4, (t1)
+ REG_S t4, (t1)
+ PTR_ADDIU t1, t1, SZREG
+ PTR_ADDIU t2, t2, SZREG
+ bne t1, t3, 1b
+ PTR_L t1, PBE_NEXT(t1)
+ bnez t1, 0
+ END(swsusp_arch_resume)
diff --git a/arch/mips/kernel/swsusp.c b/arch/mips/kernel/swsusp.c
new file mode 100644
index 0000000..864dd49
--- /dev/null
+++ b/arch/mips/kernel/swsusp.c
@@ -0,0 +1,30 @@
+/*
+ * Suspend support specific for power.
+ *
+ * Distribute under GPLv2
+ *
+ * Copyright (c) 2002 Pavel Machek <pavel@suse.cz>
+ * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
+ */
+
+#include <asm/page.h>
+
+/* References to section boundaries */
+extern const void __nosave_begin, __nosave_end;
+
+void save_processor_state(void)
+{
+ /* ... */
+}
+
+void restore_processor_state(void)
+{
+ /* ... */
+}
+
+int pfn_is_nosave(unsigned long pfn)
+{
+ unsigned long nosave_begin_pfn = __pa(&__nosave_begin) >> PAGE_SHIFT;
+ unsigned long nosave_end_pfn = PAGE_ALIGN(__pa(&__nosave_end)) >> PAGE_SHIFT;
+ return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn);
+}
diff --git a/include/asm-mips/suspend.h b/include/asm-mips/suspend.h
index 2562f8f..ee5e679 100644
--- a/include/asm-mips/suspend.h
+++ b/include/asm-mips/suspend.h
@@ -1,6 +1,9 @@
#ifndef __ASM_SUSPEND_H
#define __ASM_SUSPEND_H
-/* Somewhen... Maybe :-) */
+static inline int arch_prepare_suspend(void)
+{
+ return 0;
+}
#endif /* __ASM_SUSPEND_H */
diff --git a/include/linux/suspend.h b/include/linux/suspend.h
index 4360e08..854b7a9 100644
--- a/include/linux/suspend.h
+++ b/include/linux/suspend.h
@@ -1,7 +1,7 @@
#ifndef _LINUX_SUSPEND_H
#define _LINUX_SUSPEND_H
-#if defined(CONFIG_X86) || defined(CONFIG_FRV) || defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
+#if defined(CONFIG_X86) || defined(CONFIG_FRV) || defined(CONFIG_PPC32) || defined(CONFIG_PPC64) || defined(CONFIG_MIPS)
#include <asm/suspend.h>
#endif
#include <linux/swap.h>
diff --git a/kernel/power/Kconfig b/kernel/power/Kconfig
index 8e186c6..444f835 100644
--- a/kernel/power/Kconfig
+++ b/kernel/power/Kconfig
@@ -99,13 +99,13 @@ config SUSPEND
config HIBERNATION_UP_POSSIBLE
bool
- depends on X86 || PPC64_SWSUSP || PPC32
+ depends on MIPS || X86 || PPC64_SWSUSP || PPC32
depends on !SMP
default y
config HIBERNATION_SMP_POSSIBLE
bool
- depends on (X86 && !X86_VOYAGER) || PPC64_SWSUSP
+ depends on MIPS || (X86 && !X86_VOYAGER) || PPC64_SWSUSP
depends on SMP
default y
^ permalink raw reply related
* Re: WAIT vs. tickless kernel
From: Ralf Baechle @ 2007-10-31 16:39 UTC (permalink / raw)
To: Atsushi Nemoto; +Cc: linux-mips
In-Reply-To: <20071101.013124.108121433.anemo@mba.ocn.ne.jp>
On Thu, Nov 01, 2007 at 01:31:24AM +0900, Atsushi Nemoto wrote:
> On Wed, 31 Oct 2007 16:13:33 +0000, Ralf Baechle <ralf@linux-mips.org> wrote:
> > This one is definately playing with the fire. Or alternatively requires
> > detailed knowledge of the pipeline and pipelines tend to change. MIPS
> > Technologies does regular maintenance releases of its cores which also
> > add features and may change the pipelines in subtle way that may break
> > something like this.
>
> Yes, I never think this is robust or guaranteed...
>
> > The only safe but ugly workaround is to change the return from exception
> > code to detect if the EPC is in the range startin from the condition
> > check in the idle loop to including the WAIT instruction and if so to
> > patch the EPC to resume execution at the condition check or the
> > instruction following the WAIT.
>
> I'm also thinking of this approach. Still wondering if it is worth to
> implement.
The tickless kernel is very interesting for the low power fraction. And
it's especially those users who would suffer most the loss of the ability
to use the WAIT instruction. For a system running from two AAA cells the
tradeoff is clear ... So I think it's become a must.
Ralf
^ permalink raw reply
* Re: [PATCH] Fix SWARM build failure
From: Ralf Baechle @ 2007-10-31 16:31 UTC (permalink / raw)
To: Thiemo Seufer; +Cc: linux-mips
In-Reply-To: <20071031162656.GJ7712@networkno.de>
On Wed, Oct 31, 2007 at 04:26:56PM +0000, Thiemo Seufer wrote:
> This fixes a typo, the warning lets the build fail.
Well, there is difference between a pointer and it's address after all.
So it's good if gcc makes loud noise about it.
Ralf
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox