[PATCH] mmc: sdhci-msm: Add quirk to disable CQE for ICE legacy mode

[PATCH] mmc: sdhci-msm: Add quirk to disable CQE for ICE legacy mode

[Md Sadre Alam]

Some hosts require Inline Crypto Engine (ICE) to operate in legacy mode
instead of Command Queue Engine (CQE) mode for platform-specific
requirements or compatibility reasons. Introduce a host-level quirk
`host_disable_cqe` to forcefully disable CQE negotiation and allow ICE
to function through the legacy request path.

When the device tree omits the "supports-cqe" property, the driver sets
`host_disable_cqe = true` and avoids enabling MMC_CAP2_CQE during card
initialization. This ensures that even CQE-capable hardware falls back
to legacy SDHCI request handling. A minimal `cqhci_disable_ops` is
provided with `.cqe_enable = cqhci_host_disable` returning -EINVAL to
force the fallback. Other ops are left NULL for safe defaults.

For builds without CONFIG_MMC_CRYPTO, the driver uses standard
sdhci_add_host() to avoid unnecessary CQE infrastructure initialization.

This allows platforms to forcefully opt out of CQE usage and ensure ICE
operates reliably in legacy mode, providing stable crypto operations
without command queuing complexity.

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 drivers/mmc/host/cqhci-core.c | 28 +++++++++++++++++++++++++++-
 drivers/mmc/host/sdhci-msm.c  | 20 +++++++++++++++-----
 include/linux/mmc/host.h      |  1 +
 3 files changed, 43 insertions(+), 6 deletions(-)

diff --git a/drivers/mmc/host/cqhci-core.c b/drivers/mmc/host/cqhci-core.c
index 178277d90c31..32da3b856db1 100644
--- a/drivers/mmc/host/cqhci-core.c
+++ b/drivers/mmc/host/cqhci-core.c
@@ -334,6 +334,12 @@ int cqhci_resume(struct mmc_host *mmc)
 }
 EXPORT_SYMBOL(cqhci_resume);
 
+static int cqhci_host_disable(struct mmc_host *mmc, struct mmc_card *card)
+{
+	pr_info("%s: Host does not want to use CMDQ\n", mmc_hostname(mmc));
+	return -EINVAL;
+}
+
 static int cqhci_enable(struct mmc_host *mmc, struct mmc_card *card)
 {
 	struct cqhci_host *cq_host = mmc->cqe_private;
@@ -1135,6 +1141,18 @@ static const struct mmc_cqe_ops cqhci_cqe_ops = {
 	.cqe_recovery_finish = cqhci_recovery_finish,
 };
 
+static const struct mmc_cqe_ops cqhci_disable_ops = {
+	.cqe_enable = cqhci_host_disable,
+	.cqe_disable = NULL,
+	.cqe_request = NULL,
+	.cqe_post_req = NULL,
+	.cqe_off = NULL,
+	.cqe_wait_for_idle = NULL,
+	.cqe_timeout = NULL,
+	.cqe_recovery_start = NULL,
+	.cqe_recovery_finish = NULL,
+};
+
 struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev)
 {
 	struct cqhci_host *cq_host;
@@ -1188,7 +1206,15 @@ int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc,
 	cq_host->num_slots = NUM_SLOTS;
 	cq_host->dcmd_slot = DCMD_SLOT;
 
-	mmc->cqe_ops = &cqhci_cqe_ops;
+	/*
+	 * Some platforms may not support CQE reliably.
+	 * Use host_disable_cqe to force fallback to
+	 * legacy request path.
+	 */
+	if (mmc->host_disable_cqe)
+		mmc->cqe_ops = &cqhci_disable_ops;
+	else
+		mmc->cqe_ops = &cqhci_cqe_ops;
 
 	mmc->cqe_qdepth = NUM_SLOTS;
 	if (mmc->caps2 & MMC_CAP2_CQE_DCMD)
diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index da356627d9de..3295e8c9650b 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -2200,6 +2200,7 @@ static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
 #endif
 };
 
+#ifdef CONFIG_MMC_CRYPTO
 static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
 				struct platform_device *pdev)
 {
@@ -2228,7 +2229,8 @@ static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
 		goto cleanup;
 	}
 
-	msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
+	if (!msm_host->mmc->host_disable_cqe)
+		msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
 	cq_host->ops = &sdhci_msm_cqhci_ops;
 
 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
@@ -2270,6 +2272,7 @@ static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
 	sdhci_cleanup_host(host);
 	return ret;
 }
+#endif
 
 /*
  * Platform specific register write functions. This is so that, if any
@@ -2852,10 +2855,17 @@ static int sdhci_msm_probe(struct platform_device *pdev)
 	host->mmc_host_ops.start_signal_voltage_switch =
 		sdhci_msm_start_signal_voltage_switch;
 	host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
-	if (of_property_read_bool(node, "supports-cqe"))
-		ret = sdhci_msm_cqe_add_host(host, pdev);
-	else
-		ret = sdhci_add_host(host);
+	/*
+	 * If "supports-cqe" is not set in DT, disable CQE at host level.
+	 * This allows ICE to operate in legacy mode.
+	 */
+	msm_host->mmc->host_disable_cqe = !of_property_read_bool(node,
+								 "supports-cqe");
+#ifdef CONFIG_MMC_CRYPTO
+	ret = sdhci_msm_cqe_add_host(host, pdev);
+#else
+	ret = sdhci_add_host(host);
+#endif
 	if (ret)
 		goto pm_runtime_disable;
 
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index e0e2c265e5d1..8b963ccbda19 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -565,6 +565,7 @@ struct mmc_host {
 	int			cqe_qdepth;
 	bool			cqe_enabled;
 	bool			cqe_on;
+	bool			host_disable_cqe;
 
 	/* Inline encryption support */
 #ifdef CONFIG_MMC_CRYPTO
-- 
2.34.1

Re: [PATCH] mmc: sdhci-msm: Add quirk to disable CQE for ICE legacy mode

[kernel test robot]

Hi Md,

kernel test robot noticed the following build warnings:

[auto build test WARNING on linus/master]
[also build test WARNING on ulf-hansson-mmc-mirror/next v6.19-rc2 next-20251219]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Md-Sadre-Alam/mmc-sdhci-msm-Add-quirk-to-disable-CQE-for-ICE-legacy-mode/20251224-181537
base:   linus/master
patch link:    https://lore.kernel.org/r/20251224101050.3497746-1-quic_mdalam%40quicinc.com
patch subject: [PATCH] mmc: sdhci-msm: Add quirk to disable CQE for ICE legacy mode
config: arc-randconfig-002-20251225 (https://download.01.org/0day-ci/archive/20251225/202512251043.unAN2IJ5-lkp@intel.com/config)
compiler: arc-linux-gcc (GCC) 11.5.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251225/202512251043.unAN2IJ5-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512251043.unAN2IJ5-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/mmc/host/sdhci-msm.c:2121:36: warning: 'sdhci_msm_cqhci_ops' defined but not used [-Wunused-const-variable=]
    2121 | static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
         |                                    ^~~~~~~~~~~~~~~~~~~


vim +/sdhci_msm_cqhci_ops +2121 drivers/mmc/host/sdhci-msm.c

67b13f3e221ed8 Shaik Sajida Bhanu 2021-07-16  2120  
87a8df0dce6ad0 Ritesh Harjani     2020-01-16 @2121  static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
c93767cf64ebf4 Eric Biggers       2021-01-25  2122  	.enable		= sdhci_msm_cqe_enable,
87a8df0dce6ad0 Ritesh Harjani     2020-01-16  2123  	.disable	= sdhci_msm_cqe_disable,
c93767cf64ebf4 Eric Biggers       2021-01-25  2124  #ifdef CONFIG_MMC_CRYPTO
741521fa273fdd Eric Biggers       2024-12-12  2125  	.uses_custom_crypto_profile = true,
c93767cf64ebf4 Eric Biggers       2021-01-25  2126  #endif
87a8df0dce6ad0 Ritesh Harjani     2020-01-16  2127  };
87a8df0dce6ad0 Ritesh Harjani     2020-01-16  2128  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH] mmc: sdhci-msm: Add quirk to disable CQE for ICE legacy mode

[kernel test robot]

Hi Md,

kernel test robot noticed the following build warnings:

[auto build test WARNING on linus/master]
[also build test WARNING on ulf-hansson-mmc-mirror/next v6.19-rc2 next-20251219]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Md-Sadre-Alam/mmc-sdhci-msm-Add-quirk-to-disable-CQE-for-ICE-legacy-mode/20251224-181537
base:   linus/master
patch link:    https://lore.kernel.org/r/20251224101050.3497746-1-quic_mdalam%40quicinc.com
patch subject: [PATCH] mmc: sdhci-msm: Add quirk to disable CQE for ICE legacy mode
config: arm64-randconfig-004-20251225 (https://download.01.org/0day-ci/archive/20251225/202512251242.zOsGwwe8-lkp@intel.com/config)
compiler: clang version 22.0.0git (https://github.com/llvm/llvm-project 4ef602d446057dabf5f61fb221669ecbeda49279)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251225/202512251242.zOsGwwe8-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512251242.zOsGwwe8-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/mmc/host/sdhci-msm.c:2121:36: warning: unused variable 'sdhci_msm_cqhci_ops' [-Wunused-const-variable]
    2121 | static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
         |                                    ^~~~~~~~~~~~~~~~~~~
   1 warning generated.


vim +/sdhci_msm_cqhci_ops +2121 drivers/mmc/host/sdhci-msm.c

67b13f3e221ed8 Shaik Sajida Bhanu 2021-07-16  2120  
87a8df0dce6ad0 Ritesh Harjani     2020-01-16 @2121  static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
c93767cf64ebf4 Eric Biggers       2021-01-25  2122  	.enable		= sdhci_msm_cqe_enable,
87a8df0dce6ad0 Ritesh Harjani     2020-01-16  2123  	.disable	= sdhci_msm_cqe_disable,
c93767cf64ebf4 Eric Biggers       2021-01-25  2124  #ifdef CONFIG_MMC_CRYPTO
741521fa273fdd Eric Biggers       2024-12-12  2125  	.uses_custom_crypto_profile = true,
c93767cf64ebf4 Eric Biggers       2021-01-25  2126  #endif
87a8df0dce6ad0 Ritesh Harjani     2020-01-16  2127  };
87a8df0dce6ad0 Ritesh Harjani     2020-01-16  2128  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH] mmc: sdhci-msm: Add quirk to disable CQE for ICE legacy mode

[Eric Biggers]

On Wed, Dec 24, 2025 at 03:40:50PM +0530, Md Sadre Alam wrote:
> Some hosts require Inline Crypto Engine (ICE) to operate in legacy mode
> instead of Command Queue Engine (CQE) mode for platform-specific
> requirements or compatibility reasons. Introduce a host-level quirk
> `host_disable_cqe` to forcefully disable CQE negotiation and allow ICE
> to function through the legacy request path.
> 
> When the device tree omits the "supports-cqe" property, the driver sets
> `host_disable_cqe = true` and avoids enabling MMC_CAP2_CQE during card
> initialization. This ensures that even CQE-capable hardware falls back
> to legacy SDHCI request handling. A minimal `cqhci_disable_ops` is
> provided with `.cqe_enable = cqhci_host_disable` returning -EINVAL to
> force the fallback. Other ops are left NULL for safe defaults.
> 
> For builds without CONFIG_MMC_CRYPTO, the driver uses standard
> sdhci_add_host() to avoid unnecessary CQE infrastructure initialization.
> 
> This allows platforms to forcefully opt out of CQE usage and ensure ICE
> operates reliably in legacy mode, providing stable crypto operations
> without command queuing complexity.
> 
> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>

I'm confused.  If CQE isn't supported by the hardware, surely it would
make more sense for the driver to not advertise the host as being
CQE-capable at all?  This patch seems to introduce an ambiguous middle
ground, where the host is CQE-capable but not really.

- Eric

Re: [PATCH] mmc: sdhci-msm: Add quirk to disable CQE for ICE legacy mode

[Md Sadre Alam]

Hi,

On 12/29/2025 1:50 AM, Eric Biggers wrote:
> On Wed, Dec 24, 2025 at 03:40:50PM +0530, Md Sadre Alam wrote:
>> Some hosts require Inline Crypto Engine (ICE) to operate in legacy mode
>> instead of Command Queue Engine (CQE) mode for platform-specific
>> requirements or compatibility reasons. Introduce a host-level quirk
>> `host_disable_cqe` to forcefully disable CQE negotiation and allow ICE
>> to function through the legacy request path.
>>
>> When the device tree omits the "supports-cqe" property, the driver sets
>> `host_disable_cqe = true` and avoids enabling MMC_CAP2_CQE during card
>> initialization. This ensures that even CQE-capable hardware falls back
>> to legacy SDHCI request handling. A minimal `cqhci_disable_ops` is
>> provided with `.cqe_enable = cqhci_host_disable` returning -EINVAL to
>> force the fallback. Other ops are left NULL for safe defaults.
>>
>> For builds without CONFIG_MMC_CRYPTO, the driver uses standard
>> sdhci_add_host() to avoid unnecessary CQE infrastructure initialization.
>>
>> This allows platforms to forcefully opt out of CQE usage and ensure ICE
>> operates reliably in legacy mode, providing stable crypto operations
>> without command queuing complexity.
>>
>> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> 
> I'm confused.  If CQE isn't supported by the hardware, surely it would
> make more sense for the driver to not advertise the host as being
> CQE-capable at all?  This patch seems to introduce an ambiguous middle
> ground, where the host is CQE-capable but not really.
The hardware supports CQE: both the SDHCI‑MSM controller and the eMMC 
device are CQE‑capable.
The issue arises because the ICE driver is tightly coupled with the CMDQ 
(CQE) driver code, creating a dependency.
If the host forcefully disables CMDQ, ICE becomes unusable under the 
current design.
This patch allows ICE to remain functional via the legacy SDHCI path 
even when CMDQ is explicitly disabled by the host.

Thanks,
Alam.

Re: [PATCH] mmc: sdhci-msm: Add quirk to disable CQE for ICE legacy mode

[Adrian Hunter]

On 24/12/2025 12:10, Md Sadre Alam wrote:
> Some hosts require Inline Crypto Engine (ICE) to operate in legacy mode
> instead of Command Queue Engine (CQE) mode for platform-specific
> requirements or compatibility reasons. Introduce a host-level quirk
> `host_disable_cqe` to forcefully disable CQE negotiation and allow ICE
> to function through the legacy request path.
> 
> When the device tree omits the "supports-cqe" property, the driver sets
> `host_disable_cqe = true` and avoids enabling MMC_CAP2_CQE during card
> initialization. This ensures that even CQE-capable hardware falls back
> to legacy SDHCI request handling. A minimal `cqhci_disable_ops` is
> provided with `.cqe_enable = cqhci_host_disable` returning -EINVAL to
> force the fallback. Other ops are left NULL for safe defaults.
> 
> For builds without CONFIG_MMC_CRYPTO, the driver uses standard
> sdhci_add_host() to avoid unnecessary CQE infrastructure initialization.
> 
> This allows platforms to forcefully opt out of CQE usage and ensure ICE
> operates reliably in legacy mode, providing stable crypto operations
> without command queuing complexity.

Can't the driver simply opt-out by not setting MMC_CAP2_CQE?

> 
> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> ---
>  drivers/mmc/host/cqhci-core.c | 28 +++++++++++++++++++++++++++-
>  drivers/mmc/host/sdhci-msm.c  | 20 +++++++++++++++-----
>  include/linux/mmc/host.h      |  1 +
>  3 files changed, 43 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/mmc/host/cqhci-core.c b/drivers/mmc/host/cqhci-core.c
> index 178277d90c31..32da3b856db1 100644
> --- a/drivers/mmc/host/cqhci-core.c
> +++ b/drivers/mmc/host/cqhci-core.c
> @@ -334,6 +334,12 @@ int cqhci_resume(struct mmc_host *mmc)
>  }
>  EXPORT_SYMBOL(cqhci_resume);
>  
> +static int cqhci_host_disable(struct mmc_host *mmc, struct mmc_card *card)
> +{
> +	pr_info("%s: Host does not want to use CMDQ\n", mmc_hostname(mmc));
> +	return -EINVAL;
> +}
> +
>  static int cqhci_enable(struct mmc_host *mmc, struct mmc_card *card)
>  {
>  	struct cqhci_host *cq_host = mmc->cqe_private;
> @@ -1135,6 +1141,18 @@ static const struct mmc_cqe_ops cqhci_cqe_ops = {
>  	.cqe_recovery_finish = cqhci_recovery_finish,
>  };
>  
> +static const struct mmc_cqe_ops cqhci_disable_ops = {
> +	.cqe_enable = cqhci_host_disable,
> +	.cqe_disable = NULL,
> +	.cqe_request = NULL,
> +	.cqe_post_req = NULL,
> +	.cqe_off = NULL,
> +	.cqe_wait_for_idle = NULL,
> +	.cqe_timeout = NULL,
> +	.cqe_recovery_start = NULL,
> +	.cqe_recovery_finish = NULL,
> +};
> +
>  struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev)
>  {
>  	struct cqhci_host *cq_host;
> @@ -1188,7 +1206,15 @@ int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc,
>  	cq_host->num_slots = NUM_SLOTS;
>  	cq_host->dcmd_slot = DCMD_SLOT;
>  
> -	mmc->cqe_ops = &cqhci_cqe_ops;
> +	/*
> +	 * Some platforms may not support CQE reliably.
> +	 * Use host_disable_cqe to force fallback to
> +	 * legacy request path.
> +	 */
> +	if (mmc->host_disable_cqe)
> +		mmc->cqe_ops = &cqhci_disable_ops;
> +	else
> +		mmc->cqe_ops = &cqhci_cqe_ops;
>  
>  	mmc->cqe_qdepth = NUM_SLOTS;
>  	if (mmc->caps2 & MMC_CAP2_CQE_DCMD)
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index da356627d9de..3295e8c9650b 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -2200,6 +2200,7 @@ static const struct cqhci_host_ops sdhci_msm_cqhci_ops = {
>  #endif
>  };
>  
> +#ifdef CONFIG_MMC_CRYPTO
>  static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
>  				struct platform_device *pdev)
>  {
> @@ -2228,7 +2229,8 @@ static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
>  		goto cleanup;
>  	}
>  
> -	msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
> +	if (!msm_host->mmc->host_disable_cqe)
> +		msm_host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
>  	cq_host->ops = &sdhci_msm_cqhci_ops;
>  
>  	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
> @@ -2270,6 +2272,7 @@ static int sdhci_msm_cqe_add_host(struct sdhci_host *host,
>  	sdhci_cleanup_host(host);
>  	return ret;
>  }
> +#endif
>  
>  /*
>   * Platform specific register write functions. This is so that, if any
> @@ -2852,10 +2855,17 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>  	host->mmc_host_ops.start_signal_voltage_switch =
>  		sdhci_msm_start_signal_voltage_switch;
>  	host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning;
> -	if (of_property_read_bool(node, "supports-cqe"))
> -		ret = sdhci_msm_cqe_add_host(host, pdev);
> -	else
> -		ret = sdhci_add_host(host);
> +	/*
> +	 * If "supports-cqe" is not set in DT, disable CQE at host level.
> +	 * This allows ICE to operate in legacy mode.
> +	 */
> +	msm_host->mmc->host_disable_cqe = !of_property_read_bool(node,
> +								 "supports-cqe");
> +#ifdef CONFIG_MMC_CRYPTO
> +	ret = sdhci_msm_cqe_add_host(host, pdev);
> +#else
> +	ret = sdhci_add_host(host);
> +#endif
>  	if (ret)
>  		goto pm_runtime_disable;
>  
> diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
> index e0e2c265e5d1..8b963ccbda19 100644
> --- a/include/linux/mmc/host.h
> +++ b/include/linux/mmc/host.h
> @@ -565,6 +565,7 @@ struct mmc_host {
>  	int			cqe_qdepth;
>  	bool			cqe_enabled;
>  	bool			cqe_on;
> +	bool			host_disable_cqe;
>  
>  	/* Inline encryption support */
>  #ifdef CONFIG_MMC_CRYPTO

Re: [PATCH] mmc: sdhci-msm: Add quirk to disable CQE for ICE legacy mode

[Md Sadre Alam]

HI,

On 1/5/2026 8:31 PM, Adrian Hunter wrote:
> On 24/12/2025 12:10, Md Sadre Alam wrote:
>> Some hosts require Inline Crypto Engine (ICE) to operate in legacy mode
>> instead of Command Queue Engine (CQE) mode for platform-specific
>> requirements or compatibility reasons. Introduce a host-level quirk
>> `host_disable_cqe` to forcefully disable CQE negotiation and allow ICE
>> to function through the legacy request path.
>>
>> When the device tree omits the "supports-cqe" property, the driver sets
>> `host_disable_cqe = true` and avoids enabling MMC_CAP2_CQE during card
>> initialization. This ensures that even CQE-capable hardware falls back
>> to legacy SDHCI request handling. A minimal `cqhci_disable_ops` is
>> provided with `.cqe_enable = cqhci_host_disable` returning -EINVAL to
>> force the fallback. Other ops are left NULL for safe defaults.
>>
>> For builds without CONFIG_MMC_CRYPTO, the driver uses standard
>> sdhci_add_host() to avoid unnecessary CQE infrastructure initialization.
>>
>> This allows platforms to forcefully opt out of CQE usage and ensure ICE
>> operates reliably in legacy mode, providing stable crypto operations
>> without command queuing complexity.
> 
> Can't the driver simply opt-out by not setting MMC_CAP2_CQE?
Correct. This change is intended for the case where both host and device 
supports CMDQ, but the host explicitly wants to disable CMDQ and want to 
use the Inline Crypto Engine (ICE) in legacy way.Simply clearing 
MMC_CAP2_CQE would bypass CMDQ, but it would also bypass ICE as well.

Thanks,
Alam.

Re: [PATCH] mmc: sdhci-msm: Add quirk to disable CQE for ICE legacy mode

[Adrian Hunter]

On 07/01/2026 13:55, Md Sadre Alam wrote:
> HI,
> 
> On 1/5/2026 8:31 PM, Adrian Hunter wrote:
>> On 24/12/2025 12:10, Md Sadre Alam wrote:
>>> Some hosts require Inline Crypto Engine (ICE) to operate in legacy mode
>>> instead of Command Queue Engine (CQE) mode for platform-specific
>>> requirements or compatibility reasons. Introduce a host-level quirk
>>> `host_disable_cqe` to forcefully disable CQE negotiation and allow ICE
>>> to function through the legacy request path.
>>>
>>> When the device tree omits the "supports-cqe" property, the driver sets
>>> `host_disable_cqe = true` and avoids enabling MMC_CAP2_CQE during card
>>> initialization. This ensures that even CQE-capable hardware falls back
>>> to legacy SDHCI request handling. A minimal `cqhci_disable_ops` is
>>> provided with `.cqe_enable = cqhci_host_disable` returning -EINVAL to
>>> force the fallback. Other ops are left NULL for safe defaults.
>>>
>>> For builds without CONFIG_MMC_CRYPTO, the driver uses standard
>>> sdhci_add_host() to avoid unnecessary CQE infrastructure initialization.
>>>
>>> This allows platforms to forcefully opt out of CQE usage and ensure ICE
>>> operates reliably in legacy mode, providing stable crypto operations
>>> without command queuing complexity.
>>
>> Can't the driver simply opt-out by not setting MMC_CAP2_CQE?
> Correct. This change is intended for the case where both host and device supports CMDQ, but the host explicitly wants to disable CMDQ and want to use the Inline Crypto Engine (ICE) in legacy way.Simply clearing MMC_CAP2_CQE would bypass CMDQ, but it would also bypass ICE as well.

Did you try it?  Looks to me like removing MMC_CAP2_CQE is all that is needed since "mmc: sdhci-msm: Enable ICE for CQE-capable controllers with non-CQE cards"

Re: [PATCH] mmc: sdhci-msm: Add quirk to disable CQE for ICE legacy mode

[Md Sadre Alam]

Hi,

On 1/7/2026 7:33 PM, Adrian Hunter wrote:
> On 07/01/2026 13:55, Md Sadre Alam wrote:
>> HI,
>>
>> On 1/5/2026 8:31 PM, Adrian Hunter wrote:
>>> On 24/12/2025 12:10, Md Sadre Alam wrote:
>>>> Some hosts require Inline Crypto Engine (ICE) to operate in legacy mode
>>>> instead of Command Queue Engine (CQE) mode for platform-specific
>>>> requirements or compatibility reasons. Introduce a host-level quirk
>>>> `host_disable_cqe` to forcefully disable CQE negotiation and allow ICE
>>>> to function through the legacy request path.
>>>>
>>>> When the device tree omits the "supports-cqe" property, the driver sets
>>>> `host_disable_cqe = true` and avoids enabling MMC_CAP2_CQE during card
>>>> initialization. This ensures that even CQE-capable hardware falls back
>>>> to legacy SDHCI request handling. A minimal `cqhci_disable_ops` is
>>>> provided with `.cqe_enable = cqhci_host_disable` returning -EINVAL to
>>>> force the fallback. Other ops are left NULL for safe defaults.
>>>>
>>>> For builds without CONFIG_MMC_CRYPTO, the driver uses standard
>>>> sdhci_add_host() to avoid unnecessary CQE infrastructure initialization.
>>>>
>>>> This allows platforms to forcefully opt out of CQE usage and ensure ICE
>>>> operates reliably in legacy mode, providing stable crypto operations
>>>> without command queuing complexity.
>>>
>>> Can't the driver simply opt-out by not setting MMC_CAP2_CQE?
>> Correct. This change is intended for the case where both host and device supports CMDQ, but the host explicitly wants to disable CMDQ and want to use the Inline Crypto Engine (ICE) in legacy way.Simply clearing MMC_CAP2_CQE would bypass CMDQ, but it would also bypass ICE as well.
> 
> Did you try it?  Looks to me like removing MMC_CAP2_CQE is all that is needed since "mmc: sdhci-msm: Enable ICE for CQE-capable controllers with non-CQE cards"
I will test with MMC_CAP2_CQE removed as you indicated and share the
results.

Thanks,
Alam.