[PATCH RFC/RFT 0/2] Enable 64-bit polling mode for R-Car Gen3 and

[PATCH RFC/RFT 0/2] Enable 64-bit polling mode for R-Car Gen3 and

[Biju Das]

As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
During testing it is found that, if the DMA buffer is not aligned to 128
bit it fallback to PIO mode. In such cases, 64-bit access is much more
efficient than the current 16-bit.

Biju Das (2):
  mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode
  mmc: renesas_sdhi: Enable 64-bit polling mode

 drivers/mmc/host/renesas_sdhi_internal_dmac.c |  3 +-
 drivers/mmc/host/tmio_mmc.h                   | 12 +++++++
 drivers/mmc/host/tmio_mmc_core.c              | 32 +++++++++++++++++++
 include/linux/platform_data/tmio.h            |  3 ++
 4 files changed, 49 insertions(+), 1 deletion(-)

-- 
2.43.0

[PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode

[Biju Das]

As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
During testing it is found that, if the DMA buffer is not aligned to 128
bit it fallback to PIO mode. In such cases, 64-bit access is much more
efficient than the current 16-bit.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/mmc/host/tmio_mmc.h        | 12 +++++++++++
 drivers/mmc/host/tmio_mmc_core.c   | 32 ++++++++++++++++++++++++++++++
 include/linux/platform_data/tmio.h |  3 +++
 3 files changed, 47 insertions(+)

diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index d730b7633ae1..823143a98941 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -242,6 +242,18 @@ static inline void sd_ctrl_read32_rep(struct tmio_mmc_host *host, int addr,
 	ioread32_rep(host->ctl + (addr << host->bus_shift), buf, count);
 }
 
+static inline void sd_ctrl_read64_rep(struct tmio_mmc_host *host, int addr,
+				      u64 *buf, int count)
+{
+	ioread64_rep(host->ctl + (addr << host->bus_shift), buf, count);
+}
+
+static inline void sd_ctrl_write64_rep(struct tmio_mmc_host *host, int addr,
+				       const u64 *buf, int count)
+{
+	iowrite64_rep(host->ctl + (addr << host->bus_shift), buf, count);
+}
+
 static inline void sd_ctrl_write16(struct tmio_mmc_host *host, int addr,
 				   u16 val)
 {
diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 2cec463b5e00..c4eacf9545ba 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -350,6 +350,38 @@ static void tmio_mmc_transfer_data(struct tmio_mmc_host *host,
 	/*
 	 * Transfer the data
 	 */
+
+	if (host->pdata->flags & TMIO_MMC_64BIT_DATA_PORT) {
+		u64 *buf64 = (u64 *)buf;
+		u64 data = 0;
+
+		if (count >= 8) {
+			if (is_read)
+				sd_ctrl_read64_rep(host, CTL_SD_DATA_PORT,
+						   buf64, count >> 3);
+			else
+				sd_ctrl_write64_rep(host, CTL_SD_DATA_PORT,
+						    buf64, count >> 3);
+		}
+
+		/* if count was multiple of 8 */
+		if (!(count & 0x7))
+			return;
+
+		buf64 += count >> 3;
+		count %= 8;
+
+		if (is_read) {
+			sd_ctrl_read64_rep(host, CTL_SD_DATA_PORT, &data, 1);
+			memcpy(buf64, &data, count);
+		} else {
+			memcpy(&data, buf64, count);
+			sd_ctrl_write64_rep(host, CTL_SD_DATA_PORT, &data, 1);
+		}
+
+		return;
+	}
+
 	if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) {
 		u32 data = 0;
 		u32 *buf32 = (u32 *)buf;
diff --git a/include/linux/platform_data/tmio.h b/include/linux/platform_data/tmio.h
index b060124ba1ae..426291713b83 100644
--- a/include/linux/platform_data/tmio.h
+++ b/include/linux/platform_data/tmio.h
@@ -47,6 +47,9 @@
 /* Some controllers have a CBSY bit */
 #define TMIO_MMC_HAVE_CBSY		BIT(11)
 
+/* Some controllers have a 64-bit wide data port register */
+#define TMIO_MMC_64BIT_DATA_PORT	BIT(12)
+
 struct tmio_mmc_data {
 	void				*chan_priv_tx;
 	void				*chan_priv_rx;
-- 
2.43.0

Re: [PATCH RFC/RFT 1/2] mmc: tmio: Add 64-bit read/write support for SD_BUF0 in polling mode

[Wolfram Sang]

On Mon, Jun 30, 2025 at 09:13:10AM +0100, Biju Das wrote:
> As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
> bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
> During testing it is found that, if the DMA buffer is not aligned to 128
> bit it fallback to PIO mode. In such cases, 64-bit access is much more
> efficient than the current 16-bit.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

[PATCH RFC/RFT 2/2] mmc: renesas_sdhi: Enable 64-bit polling mode

[Biju Das]

Enable 64-bit polling mode for R-Car gen3 and RZ/G2L SoCs.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 drivers/mmc/host/renesas_sdhi_internal_dmac.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index 4b389e92399e..9e3ed0bcddd6 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -107,7 +107,8 @@ static const struct renesas_sdhi_of_data of_data_rza2 = {
 
 static const struct renesas_sdhi_of_data of_data_rcar_gen3 = {
 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
-			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
+			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
+			  TMIO_MMC_64BIT_DATA_PORT,
 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
 			  MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
 	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
-- 
2.43.0

Re: [PATCH RFC/RFT 2/2] mmc: renesas_sdhi: Enable 64-bit polling mode

[Wolfram Sang]

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On Mon, Jun 30, 2025 at 09:13:11AM +0100, Biju Das wrote:
> Enable 64-bit polling mode for R-Car gen3 and RZ/G2L SoCs.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Same as patch 1, not tested yet, hope for tomorrow.


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Re: [PATCH RFC/RFT 2/2] mmc: renesas_sdhi: Enable 64-bit polling mode

[Wolfram Sang]

On Mon, Jun 30, 2025 at 09:13:11AM +0100, Biju Das wrote:
> Enable 64-bit polling mode for R-Car gen3 and RZ/G2L SoCs.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Re: [PATCH RFC/RFT 0/2] Enable 64-bit polling mode for R-Car Gen3 and

[Wolfram Sang]

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On Mon, Jun 30, 2025 at 09:13:09AM +0100, Biju Das wrote:
> As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
> bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
> During testing it is found that, if the DMA buffer is not aligned to 128
> bit it fallback to PIO mode. In such cases, 64-bit access is much more
> efficient than the current 16-bit.

Cool, I had this somewhere on my todo-list as well. I want to test but
it will probably be only on Friday. But looking forward to it!


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RE: [PATCH RFC/RFT 0/2] Enable 64-bit polling mode for R-Car Gen3 and

[Biju Das]

Hi Wolfram Sang,

> -----Original Message-----
> From: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Sent: 08 July 2025 21:29
> Subject: Re: [PATCH RFC/RFT 0/2] Enable 64-bit polling mode for R-Car Gen3 and
> 
> On Mon, Jun 30, 2025 at 09:13:09AM +0100, Biju Das wrote:
> > As per the RZ/{G2L,G3E} HW manual SD_BUF0 can be accessed by 16/32/64
> > bits. Most of the data transfer in SD/SDIO/eMMC mode is more than 8 bytes.
> > During testing it is found that, if the DMA buffer is not aligned to
> > 128 bit it fallback to PIO mode. In such cases, 64-bit access is much
> > more efficient than the current 16-bit.
> 
> Cool, I had this somewhere on my todo-list as well. I want to test but it will probably be only on
> Friday. But looking forward to it!

Thanks. Also, we need to find a way to handle this issue [1]

[1] https://lore.kernel.org/linux-renesas-soc/TY3PR01MB1134662BDC486D781E5B263878641A@TY3PR01MB11346.jpnprd01.prod.outlook.com/

Cheers,
Biju