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From: Jaime Liao <jaimeliao.tw@gmail.com>
To: linux-mtd@lists.infradead.org, tudor.ambarus@linaro.org,
	pratyush@kernel.org, michael@walle.cc, miquel.raynal@bootlin.com
Cc: leoyu@mxic.com.tw, jaimeliao@mxic.com.tw
Subject: [PATCH v5 3/6] mtd: spi-nor: core: Allow specifying the byte order in DTR mode
Date: Fri, 17 Nov 2023 16:38:50 +0800	[thread overview]
Message-ID: <20231117083853.33329-4-jaimeliao.tw@gmail.com> (raw)
In-Reply-To: <20231117083853.33329-1-jaimeliao.tw@gmail.com>

From: JaimeLiao <jaimeliao@mxic.com.tw>

Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR.
The byte order of 16-bit words is swapped when read or written in 8D-8D-8D
mode compared to STR modes. Allow operations to specify the byte order in
DTR mode, so that controllers can swap the bytes back at run-time to
address the flash's endianness requirements, if they are capable. If the
controllers are not capable of swapping the bytes, the protocol is
downgrade via spi_nor_spimem_adjust_hwcaps(). When available, the swapping
of the bytes is always done regardless if it's a data or register access,
so that we comply with the JESD216 requirements: "Byte order of 16-bit
words is swapped when read in 8D-8D-8D mode compared to 1-1-1".

Merge Tudor's patch and add modifications for suiting newer version
of Linux kernel.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
---
 drivers/mtd/spi-nor/core.c | 8 ++++++++
 drivers/mtd/spi-nor/core.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 1c443fe568cf..f659dd037a25 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -70,6 +70,13 @@ static u8 spi_nor_get_cmd_ext(const struct spi_nor *nor,
 	}
 }
 
+static inline bool spi_nor_is_octal_dtr_swab16(const struct spi_nor *nor,
+						enum spi_nor_protocol proto)
+{
+	return (proto == SNOR_PROTO_8_8_8_DTR) &&
+		(nor->flags & SNOR_F_DTR_SWAB16);
+}
+
 /**
  * spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op.
  * @nor:		pointer to a 'struct spi_nor'
@@ -105,6 +112,7 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor,
 		op->addr.dtr = true;
 		op->dummy.dtr = true;
 		op->data.dtr = true;
+		op->data.dtr_swab16 = spi_nor_is_octal_dtr_swab16(nor, proto);
 
 		/* 2 bytes per clock cycle in DTR mode. */
 		op->dummy.nbytes *= 2;
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 93cd2fc3606d..fe1259b32110 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -140,6 +140,7 @@ enum spi_nor_option_flags {
 	SNOR_F_RWW		= BIT(14),
 	SNOR_F_ECC		= BIT(15),
 	SNOR_F_NO_WP		= BIT(16),
+	SNOR_F_DTR_SWAB16       = BIT(17),
 };
 
 struct spi_nor_read_command {
-- 
2.25.1


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  parent reply	other threads:[~2023-11-17  8:39 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-17  8:38 [PATCH v5 0/6] Add octal DTR support for Macronix flash Jaime Liao
2023-11-17  8:38 ` [PATCH v5 1/6] mtd: spi-nor: add Octal " Jaime Liao
2023-11-17  8:38 ` [PATCH v5 2/6] spi: spi-mem: Allow specifying the byte order in DTR mode Jaime Liao
2023-11-17  9:17   ` Tudor Ambarus
2023-11-17 10:00     ` liao jaime
2023-11-17  8:38 ` Jaime Liao [this message]
2023-11-21  8:40   ` [PATCH v5 3/6] mtd: spi-nor: core: " Michael Walle
2023-11-21  9:53     ` liao jaime
2023-11-17  8:38 ` [PATCH v5 4/6] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Jaime Liao
2023-11-17  8:38 ` [PATCH v5 5/6] mtd: spi-nor: add support for Macronix Octal flash with RWW feature Jaime Liao
2023-11-17  9:21   ` Tudor Ambarus
2023-11-17 10:01     ` liao jaime
2023-11-17  8:38 ` [PATCH v5 6/6] mtd: spi-nor: add support for Macronix Octal flash Jaime Liao
2023-11-17  8:57   ` Michael Walle
2023-11-17  9:05     ` Tudor Ambarus
     [not found]     ` <CAAQoYRkw5hUONJ32sGKxgv5XtO24Vc6=KojankTG73u5E7jPBw@mail.gmail.com>
2023-11-21  8:51       ` Michael Walle
2023-11-21  9:09         ` Tudor Ambarus
2023-11-22  3:15           ` liao jaime
2023-11-22 10:16             ` Michael Walle
2023-11-17  9:23   ` Tudor Ambarus
2023-11-17  8:48 ` [PATCH v5 0/6] Add octal DTR support for Macronix flash Michael Walle
2023-11-17 10:09   ` liao jaime
2023-11-17 10:26     ` Michael Walle
2023-11-20  1:50       ` liao jaime
2023-11-21  8:29         ` Michael Walle
2023-11-21  8:32           ` liao jaime

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