From: Vignesh Raghavendra <vigneshr@ti.com>
To: Ivan Mikhaylov <i.mikhaylov@yadro.com>,
Tudor Ambarus <tudor.ambarus@microchip.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>
Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [RESEND PATCH 2/2] mtd: spi-nor: enable lock interface for macronix chips
Date: Wed, 30 Sep 2020 15:10:02 +0530 [thread overview]
Message-ID: <cb47d79f-ecbb-f0ec-388e-b56ba740045e@ti.com> (raw)
In-Reply-To: <20200921112450.4824-3-i.mikhaylov@yadro.com>
Hi,
On 9/21/20 4:54 PM, Ivan Mikhaylov wrote:
> Add locks for whole macronix chip series with BP0-2 and BP0-3 bits.
>
> Tested with mx25l51245g(BP0-3).
Since you have only tested on flash that have 4bit BP, please don't
modify flashes that have 3bit BP. Lets be conservative and enable only
things that have been tested else we may end up with broken feature from
day 1.
Regards
Vignesh
>
> Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
> ---
> drivers/mtd/spi-nor/macronix.c | 75 ++++++++++++++++++++++------------
> 1 file changed, 50 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
> index 96735d83c77c..80de43eb05d6 100644
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -37,53 +37,78 @@ static const struct flash_info macronix_parts[] = {
> /* Macronix */
> { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) },
> { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
> - { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
> - { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
> - { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
> - { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, SECT_4K) },
> - { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
> - { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, SECT_4K) },
> - { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4, SECT_4K) },
> + { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8,
> + SECT_4K | SPI_NOR_HAS_LOCK) },
> + { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16,
> + SPI_NOR_HAS_LOCK) },
> + { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32,
> + SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> + { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64,
> + SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> + { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64,
> + SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> + { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128,
> + SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> + { "mx25u2033e", INFO(0xc22532, 0, 64 * 1024, 4,
> + SECT_4K | SPI_NOR_HAS_LOCK) },
> { "mx25u3235f", INFO(0xc22536, 0, 64 * 1024, 64,
> SECT_4K | SPI_NOR_DUAL_READ |
> - SPI_NOR_QUAD_READ) },
> - { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) },
> - { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) },
> - { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
> - { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
> - { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
> + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
> + SPI_NOR_4BIT_BP) },
> + { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8,
> + SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> + { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16,
> + SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> + { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128,
> + SECT_4K | SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> + { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256,
> + SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> + { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256,
> + SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> { "mx25r3235f", INFO(0xc22816, 0, 64 * 1024, 64,
> SECT_4K | SPI_NOR_DUAL_READ |
> - SPI_NOR_QUAD_READ) },
> + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
> + SPI_NOR_4BIT_BP) },
> { "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
> SECT_4K | SPI_NOR_DUAL_READ |
> - SPI_NOR_QUAD_READ) },
> + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
> + SPI_NOR_4BIT_BP) },
> { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
> - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
> + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> + SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP)
> .fixups = &mx25l25635_fixups },
> { "mx25u25635f", INFO(0xc22539, 0, 64 * 1024, 512,
> - SECT_4K | SPI_NOR_4B_OPCODES) },
> + SECT_4K | SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
> + SPI_NOR_4BIT_BP) },
> { "mx25u51245g", INFO(0xc2253a, 0, 64 * 1024, 1024,
> SECT_4K | SPI_NOR_DUAL_READ |
> - SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
> + SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> { "mx25v8035f", INFO(0xc22314, 0, 64 * 1024, 16,
> SECT_4K | SPI_NOR_DUAL_READ |
> - SPI_NOR_QUAD_READ) },
> - { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
> + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
> + SPI_NOR_4BIT_BP) },
> + { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512,
> + SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> { "mx25l51245g", INFO(0xc2201a, 0, 64 * 1024, 1024,
> SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> - SPI_NOR_4B_OPCODES) },
> + SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
> + SPI_NOR_4BIT_BP) },
> { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024,
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
> - SPI_NOR_4B_OPCODES) },
> + SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
> + SPI_NOR_4BIT_BP) },
> { "mx66u51235f", INFO(0xc2253a, 0, 64 * 1024, 1024,
> SECT_4K | SPI_NOR_DUAL_READ |
> - SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> + SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
> + SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP) },
> { "mx66l1g45g", INFO(0xc2201b, 0, 64 * 1024, 2048,
> SECT_4K | SPI_NOR_DUAL_READ |
> - SPI_NOR_QUAD_READ) },
> + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
> + SPI_NOR_4BIT_BP) },
> { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048,
> - SPI_NOR_QUAD_READ) },
> + SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK |
> + SPI_NOR_4BIT_BP) },
> };
>
> static void macronix_default_init(struct spi_nor *nor)
>
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2020-09-30 9:41 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-21 11:24 [RESEND PATCH 0/2] enable lock interface for macronix chips Ivan Mikhaylov
2020-09-21 11:24 ` [RESEND PATCH 1/2] mtd: spi-nor: do not touch TB bit without SPI_NOR_HAS_TB Ivan Mikhaylov
2020-09-30 9:36 ` Vignesh Raghavendra
2020-09-30 13:07 ` Ivan Mikhaylov
2020-09-30 14:00 ` Vignesh Raghavendra
2020-09-30 16:22 ` Ivan Mikhaylov
2020-09-21 11:24 ` [RESEND PATCH 2/2] mtd: spi-nor: enable lock interface for macronix chips Ivan Mikhaylov
2020-09-30 9:40 ` Vignesh Raghavendra [this message]
2020-09-30 13:09 ` Ivan Mikhaylov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=cb47d79f-ecbb-f0ec-388e-b56ba740045e@ti.com \
--to=vigneshr@ti.com \
--cc=i.mikhaylov@yadro.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mtd@lists.infradead.org \
--cc=miquel.raynal@bootlin.com \
--cc=richard@nod.at \
--cc=tudor.ambarus@microchip.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox