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From: David Fugate <david.fugate@linux.intel.com>
To: Christoph Hellwig <hch@lst.de>
Cc: kbusch@kernel.org, axboe@fb.com, sagi@grimberg.me,
	linux-nvme@lists.infradead.org, david.fugate@intel.com
Subject: Re: [PATCH] nvme: associate stripe size quirk with D4512
Date: Fri, 12 Jun 2020 08:43:15 -0600	[thread overview]
Message-ID: <e2c46dfec9e779d945088b025f833bcd4e29cc1e.camel@linux.intel.com> (raw)
In-Reply-To: <20200611054156.GB3518@lst.de>

On Thu, 2020-06-11 at 07:41 +0200, Christoph Hellwig wrote:
> On Wed, Jun 10, 2020 at 09:38:36PM -0600, David Fugate wrote:
> > Intel's D4512 dual-port SSD is based on the older Intel P4500 SSDs
> > whose development predated the NOIOB feature. Based on a customer
> > request, the D4512's device ID was changed from the P4500s'. This
> > patch associates D4512's device ID with the stripe size quirk to
> > improve its performance.
> 
> NAK.  We've been told Intel forever that we need a standard quirk,
> and we actually do have way to expose this information in Identify
> now.
> Just kick your firmware engineers in the but to set the trivial field
> in Identify.

Thanks for the feedback Christoph. Our FW engineer for this product is
currently on vacation, but I'll relay your suggestion to see if it's
viable.

In the meantime, I'm hearing your rejection for this is simply Intel
standardized the driver-assisted striping feature as NOIOB and failed
to realize it in any Intel product. Other than this, was there a
technical reason for rejecting this patch?

Thanks again!


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  reply	other threads:[~2020-06-12 14:43 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-11  3:38 [PATCH] nvme: associate stripe size quirk with D4512 David Fugate
2020-06-11  5:41 ` Christoph Hellwig
2020-06-12 14:43   ` David Fugate [this message]
2020-06-15  7:20     ` Christoph Hellwig
2020-07-02 21:16       ` David Fugate
2020-07-02 21:48         ` Keith Busch
2020-07-02 22:26           ` David Fugate
2020-07-03 20:16             ` Keith Busch

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