[PATCH 0/3] OMAPDSS: HDMI: Add support for audio MCLK

[PATCH 0/3] OMAPDSS: HDMI: Add support for audio MCLK

[Ricardo Neri]

Hello,

Certain OMAP4 revisions (i.e., 4430 ES2.3, 4460, and 4470) use
a pseudo clock (generated from the TMDS clock), MCLK, to drive the
generation of Audio Clock Regeneration packets. Other devices
(i.e., 4430 ES2.[0,2]) use the TMDS clock directly. 

This set of patches introduces functionality to enable the MCLK on the
relevant devices. Such clock is added as new DSS feature. The dss_features
structures are rearranged to reflect the MCLK support across several
silicon revisions.

These patches have been validated on OMAP 4430 ES2.2 and ES2.3 as well as
on 4460 ES1.0. The HDMI sinks used for validation are monitor Dell ST2210b,
AV receiver Onkyo TX-SR508 and AV receiver Yamaha RX-V367. Audio playback
is functional in all of them.

These patches are based on
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git v3.3-rc2

Ricardo Neri (3):
  OMAPDSS: Add DSS feature for HDMI MCLK for audio
  OMAPDSS: HDMI: Implement initialization of MCLK
  OMAPDSS: HDMI: Modify logic to configure MCLK

 drivers/video/omap2/dss/dss_features.c    |   31 +++++++++++++++++++++++-
 drivers/video/omap2/dss/dss_features.h    |    1 +
 drivers/video/omap2/dss/hdmi.c            |    6 +++-
 drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c |   37 +++++++++++++++++-----------
 4 files changed, 57 insertions(+), 18 deletions(-)

[PATCH 1/3] OMAPDSS: Add DSS feature for HDMI MCLK for audio

[Ricardo Neri]

Certain OMAP4 revisions (i.e., 4430 ES2.3, 4460, and 4470) use
a pseudo clock (generated from the TMDS clock), MCLK, to drive the
generation of Audio Clock Regeneration packets. Other devices
(i.e., 4430 ES2.[0,2]) use the TMDS clock directly.

This patch adds a new DSS feature for MCLK support. It also rearranges
the omap_dss_features structures to reflect the devices supporting it.

Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
---
 drivers/video/omap2/dss/dss_features.c |   31 ++++++++++++++++++++++++++++++-
 drivers/video/omap2/dss/dss_features.h |    1 +
 2 files changed, 31 insertions(+), 1 deletions(-)

diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index afcb593..162c9a9 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -432,6 +432,30 @@ static const struct omap_dss_features omap4430_es1_0_dss_features  = {
 	.burst_size_unit = 16,
 };
 
+/* For OMAP4430 ES 2.0, 2.1 and 2.2 revisions */
+static const struct omap_dss_features omap4430_es2_0_1_2_dss_features = {
+	.reg_fields = omap4_dss_reg_fields,
+	.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
+
+	.has_feature	=
+		FEAT_MGR_LCD2 |
+		FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
+		FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
+		FEAT_DSI_GNQ | FEAT_HDMI_CTS_SWMODE |
+		FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 | FEAT_CPR |
+		FEAT_PRELOAD | FEAT_FIR_COEF_V | FEAT_ALPHA_FREE_ZORDER,
+
+	.num_mgrs = 3,
+	.num_ovls = 4,
+	.supported_displays = omap4_dss_supported_displays,
+	.supported_color_modes = omap4_dss_supported_color_modes,
+	.overlay_caps = omap4_dss_overlay_caps,
+	.clksrc_names = omap4_dss_clk_source_names,
+	.dss_params = omap4_dss_param_range,
+	.buffer_size_unit = 16,
+	.burst_size_unit = 16,
+};
+
 /* For all the other OMAP4 versions */
 static const struct omap_dss_features omap4_dss_features = {
 	.reg_fields = omap4_dss_reg_fields,
@@ -443,7 +467,8 @@ static const struct omap_dss_features omap4_dss_features = {
 		FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
 		FEAT_DSI_GNQ | FEAT_HDMI_CTS_SWMODE |
 		FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2 | FEAT_CPR |
-		FEAT_PRELOAD | FEAT_FIR_COEF_V | FEAT_ALPHA_FREE_ZORDER,
+		FEAT_PRELOAD | FEAT_FIR_COEF_V | FEAT_ALPHA_FREE_ZORDER |
+		FEAT_HDMI_AUDIO_USE_MCLK,
 
 	.num_mgrs = 3,
 	.num_ovls = 4,
@@ -569,6 +594,10 @@ void dss_features_init(void)
 		omap_current_dss_features = &omap3430_dss_features;
 	else if (omap_rev() == OMAP4430_REV_ES1_0)
 		omap_current_dss_features = &omap4430_es1_0_dss_features;
+	else if (omap_rev() == OMAP4430_REV_ES2_0 ||
+		omap_rev() == OMAP4430_REV_ES2_1 ||
+		omap_rev() == OMAP4430_REV_ES2_2)
+		omap_current_dss_features = &omap4430_es2_0_1_2_dss_features;
 	else if (cpu_is_omap44xx())
 		omap_current_dss_features = &omap4_dss_features;
 	else
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index cd833bb..62dfb2e 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -58,6 +58,7 @@ enum dss_feat_id {
 	FEAT_FIR_COEF_V			= 1 << 25,
 	FEAT_ALPHA_FIXED_ZORDER		= 1 << 26,
 	FEAT_ALPHA_FREE_ZORDER		= 1 << 27,
+	FEAT_HDMI_AUDIO_USE_MCLK	= 1 << 28,
 };
 
 /* DSS register field id */
-- 
1.7.0.4

[PATCH 2/3] OMAPDSS: HDMI: Implement initialization of MCLK

[Ricardo Neri]

When the MCLK is used to drive the Audio Clock Regeneration packets,
the initialization procedure is to set ACR_CTRL[2] to 0 and then
back again to 1. Also, devices that do not support the MCLK, use
the TMDS clock directly by leaving ACR_CTRL[2] set to 0.

The MLCK clock divisor, mclk_mode, is configured only if MLCK
is used. Such configuration is no longer related to the CTS mode
as in some silicon revisions CTS SW-mode is used along with the MCLK.

Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
---
 drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c |   37 +++++++++++++++++-----------
 1 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
index 9af81f1..0150e21 100644
--- a/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
+++ b/drivers/video/omap2/dss/ti_hdmi_4xxx_ip.c
@@ -1023,13 +1023,9 @@ void hdmi_core_audio_config(struct hdmi_ip_data *ip_data,
 	u32 r;
 	void __iomem *av_base = hdmi_av_base(ip_data);
 
-	/* audio clock recovery parameters */
-	r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
-	r = FLD_MOD(r, cfg->use_mclk, 2, 2);
-	r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
-	r = FLD_MOD(r, cfg->cts_mode, 0, 0);
-	hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
-
+	/*
+	 * Parameters for generation of Audio Clock Recovery packets
+	 */
 	REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
 	REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
 	REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
@@ -1041,14 +1037,6 @@ void hdmi_core_audio_config(struct hdmi_ip_data *ip_data,
 		REG_FLD_MOD(av_base,
 				HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
 	} else {
-		/*
-		 * HDMI IP uses this configuration to divide the MCLK to
-		 * update CTS value.
-		 */
-		REG_FLD_MOD(av_base,
-				HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
-
-		/* Configure clock for audio packets */
 		REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
 				cfg->aud_par_busclk, 7, 0);
 		REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
@@ -1057,6 +1045,25 @@ void hdmi_core_audio_config(struct hdmi_ip_data *ip_data,
 				(cfg->aud_par_busclk >> 16), 7, 0);
 	}
 
+	/* Set ACR clock divisor */
+	REG_FLD_MOD(av_base,
+			HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
+
+	r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
+	/*
+	 * Use TMDS clock for ACR packets. For devices that use
+	 * the MCLK, this is the first part of the MCLK initialization.
+	 */
+	r = FLD_MOD(r, 0, 2, 2);
+
+	r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
+	r = FLD_MOD(r, cfg->cts_mode, 0, 0);
+	hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
+
+	/* For devices using MCLK, this completes its initialization. */
+	if (cfg->use_mclk)
+		REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2);
+
 	/* Override of SPDIF sample frequency with value in I2S_CHST4 */
 	REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
 						cfg->fs_override, 1, 1);
-- 
1.7.0.4

[PATCH 3/3] OMAPDSS: HDMI: Modify logic to configure MCLK

[Ricardo Neri]

The MCLK mode defines a factor to divide the clock that is used to
generate the Audio Clock Regeneration packets, MCLK.

The divisor is not used when the CTS value is calculated by HW.
When the value is calculated by SW, it depends on the silicon
revision.

Signed-off-by: Ricardo Neri <ricardo.neri@ti.com>
---
 drivers/video/omap2/dss/hdmi.c |    6 ++++--
 1 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index b4c270e..04c83c8 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -692,13 +692,15 @@ static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
 	if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
 		core_cfg.aud_par_busclk = 0;
 		core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
-		core_cfg.use_mclk = false;
+		core_cfg.use_mclk = dss_has_feature(FEAT_HDMI_AUDIO_USE_MCLK);
 	} else {
 		core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
 		core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
 		core_cfg.use_mclk = true;
-		core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
 	}
+
+	if (core_cfg.use_mclk)
+		core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
 	core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
 	core_cfg.en_spdif = false;
 	/* Use sample frequency from channel status word */
-- 
1.7.0.4

Re: [PATCH 0/3] OMAPDSS: HDMI: Add support for audio MCLK

[Tomi Valkeinen]

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Hi,

On Wed, 2012-02-08 at 21:10 -0600, Ricardo Neri wrote:
> Hello,
> 
> Certain OMAP4 revisions (i.e., 4430 ES2.3, 4460, and 4470) use
> a pseudo clock (generated from the TMDS clock), MCLK, to drive the
> generation of Audio Clock Regeneration packets. Other devices
> (i.e., 4430 ES2.[0,2]) use the TMDS clock directly. 
> 
> This set of patches introduces functionality to enable the MCLK on the
> relevant devices. Such clock is added as new DSS feature. The dss_features
> structures are rearranged to reflect the MCLK support across several
> silicon revisions.
> 
> These patches have been validated on OMAP 4430 ES2.2 and ES2.3 as well as
> on 4460 ES1.0. The HDMI sinks used for validation are monitor Dell ST2210b,
> AV receiver Onkyo TX-SR508 and AV receiver Yamaha RX-V367. Audio playback
> is functional in all of them.

One question just to be sure: are you sure this clocking difference is
based on OMAP revision, and has nothing to do with the board?

I think this looks fine. However, it doesn't apply as the dss feat stuff
has been changed. Could you rebase the patches on top of

git://gitorious.org/linux-omap-dss2/linux.git dev

 Tomi


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Re: [PATCH 0/3] OMAPDSS: HDMI: Add support for audio MCLK

[Ricardo Neri]

Hi Tomi,

On Tue, 2012-02-14 at 14:27 +0200, Tomi Valkeinen wrote:
> Hi,
> 
> On Wed, 2012-02-08 at 21:10 -0600, Ricardo Neri wrote:
> > Hello,
> > 
> > Certain OMAP4 revisions (i.e., 4430 ES2.3, 4460, and 4470) use
> > a pseudo clock (generated from the TMDS clock), MCLK, to drive the
> > generation of Audio Clock Regeneration packets. Other devices
> > (i.e., 4430 ES2.[0,2]) use the TMDS clock directly. 
> > 
> > This set of patches introduces functionality to enable the MCLK on the
> > relevant devices. Such clock is added as new DSS feature. The dss_features
> > structures are rearranged to reflect the MCLK support across several
> > silicon revisions.
> > 
> > These patches have been validated on OMAP 4430 ES2.2 and ES2.3 as well as
> > on 4460 ES1.0. The HDMI sinks used for validation are monitor Dell ST2210b,
> > AV receiver Onkyo TX-SR508 and AV receiver Yamaha RX-V367. Audio playback
> > is functional in all of them.
> 
> One question just to be sure: are you sure this clocking difference is
> based on OMAP revision, and has nothing to do with the board?

Yes, the source clock for the ACR packets depends on how the HDMI IP is
integrated into the OMAP and therefore it depends solely on the OMAP
revision and not the board.
> 
> I think this looks fine. However, it doesn't apply as the dss feat stuff
> has been changed. Could you rebase the patches on top of
> 
> git://gitorious.org/linux-omap-dss2/linux.git dev

Sure, I will rebase and resubmit.

Thanks,

Ricardo
> 
>  Tomi
>