public inbox for linux-omap@vger.kernel.org
 help / color / mirror / Atom feed
* [PATCH] mfd: twl6040: Correct HPPLL configuration for 19.2 and 38.4 MHz mclk
@ 2014-05-06  8:46 Peter Ujfalusi
  2014-05-09 10:00 ` Lee Jones
  0 siblings, 1 reply; 2+ messages in thread
From: Peter Ujfalusi @ 2014-05-06  8:46 UTC (permalink / raw)
  To: lee.jones; +Cc: linux-kernel, linux-omap, sameo

When the MCLK is 19.2 or 38.4 MHz the HPPLL need to be enabled and can be
put in bypass mode.
This will fix HPPLL use on boards with 19.2MHz mclk.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
---
 drivers/mfd/twl6040.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/mfd/twl6040.c b/drivers/mfd/twl6040.c
index 12b314ea48dc..ae26d84b3a59 100644
--- a/drivers/mfd/twl6040.c
+++ b/drivers/mfd/twl6040.c
@@ -441,12 +441,9 @@ int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
 					    TWL6040_HPLLENA;
 				break;
 			case 19200000:
-				/*
-				* PLL disabled
-				* (enable PLL if MCLK jitter quality
-				*  doesn't meet specification)
-				*/
-				hppllctl |= TWL6040_MCLK_19200KHZ;
+				/* PLL enabled, bypass mode */
+				hppllctl |= TWL6040_MCLK_19200KHZ |
+					    TWL6040_HPLLBP | TWL6040_HPLLENA;
 				break;
 			case 26000000:
 				/* PLL enabled, active mode */
@@ -454,9 +451,9 @@ int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
 					    TWL6040_HPLLENA;
 				break;
 			case 38400000:
-				/* PLL enabled, active mode */
+				/* PLL enabled, bypass mode */
 				hppllctl |= TWL6040_MCLK_38400KHZ |
-					    TWL6040_HPLLENA;
+					    TWL6040_HPLLBP | TWL6040_HPLLENA;
 				break;
 			default:
 				dev_err(twl6040->dev,
-- 
1.9.2


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] mfd: twl6040: Correct HPPLL configuration for 19.2 and 38.4 MHz mclk
  2014-05-06  8:46 [PATCH] mfd: twl6040: Correct HPPLL configuration for 19.2 and 38.4 MHz mclk Peter Ujfalusi
@ 2014-05-09 10:00 ` Lee Jones
  0 siblings, 0 replies; 2+ messages in thread
From: Lee Jones @ 2014-05-09 10:00 UTC (permalink / raw)
  To: Peter Ujfalusi; +Cc: linux-kernel, linux-omap, sameo

> When the MCLK is 19.2 or 38.4 MHz the HPPLL need to be enabled and can be
> put in bypass mode.
> This will fix HPPLL use on boards with 19.2MHz mclk.
> 
> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
> ---
>  drivers/mfd/twl6040.c | 13 +++++--------
>  1 file changed, 5 insertions(+), 8 deletions(-)

Applied, thanks.

-- 
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2014-05-09 10:00 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-05-06  8:46 [PATCH] mfd: twl6040: Correct HPPLL configuration for 19.2 and 38.4 MHz mclk Peter Ujfalusi
2014-05-09 10:00 ` Lee Jones

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox