From: James Bottomley <James.Bottomley@steeleye.com>
To: Grant Grundler <grundler@parisc-linux.org>
Cc: "M. Grabert" <xam@cs.ucc.ie>,
PARISC list <parisc-linux@lists.parisc-linux.org>,
Alan Cox <alan@lxorguk.ukuu.org.uk>
Subject: Re: [parisc-linux] C3000 and Promise Ultra100 TX2 PCI Controller
Date: 28 Feb 2004 11:24:53 -0600 [thread overview]
Message-ID: <1077989094.1968.62.camel@mulgrave> (raw)
In-Reply-To: <20040228164506.GA11659@colo.lackof.org>
On Sat, 2004-02-28 at 10:45, Grant Grundler wrote:
> include/asm/io.h:#define readw(addr) (*(volatile unsigned short *) __io_virt(addr))
>
>
> Uhoh..no swapping at all in this case.
> I was expecting readw to swap bytes.
> Am I just confused again about how a BE is supposed to behave?
> *sigh*
The rule is supposed to be that inX/outX/readX/writeX be free of
endianness issues on the bus. i.e. doing a readw() on a memory mapped
PCI config space on parisc should have a le16_to_cpu implied in the
readw().
Obviously, accesses which go straight to memory (i.e. not via accessor
macros) are the responsibility of the driver for sorting out the
endianness.
James
next prev parent reply other threads:[~2004-02-28 17:24 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-02-26 0:52 [parisc-linux] C3000 and Promise Ultra100 TX2 PCI Controller M. Grabert
2004-02-26 1:08 ` Alan Cox
2004-02-26 1:59 ` M. Grabert
[not found] ` <20040226051124.GB3645@colo.lackof.org>
[not found] ` <Pine.LNX.4.58.0402260513010.28003@sal.ucc.ie>
2004-02-26 15:56 ` Grant Grundler
2004-02-27 18:44 ` Alan Cox
2004-02-27 21:23 ` Grant Grundler
2004-02-27 23:50 ` M. Grabert
2004-02-28 1:05 ` M. Grabert
2004-02-28 16:07 ` Alan Cox
2004-02-28 16:45 ` Grant Grundler
2004-02-28 17:24 ` James Bottomley [this message]
2004-02-28 17:41 ` Matthew Wilcox
2004-02-28 19:48 ` Grant Grundler
2004-02-28 1:53 ` Matthew Wilcox
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