[hppa-linux] Qn on PA-RISC Page tables and TLB

[hppa-linux] Qn on PA-RISC Page tables and TLB

[Kumar]

PA-RISC Arch 1.1 book says:
On page 3-14:

	Exact form of these tables is s/w convention. 

Q.	If the format is software convention, does that mean
	the fields within TLB slots are not defined by Hardware ?
	Though  the book does seem to indicate what fields are needed
	in a pdir entry. Without knowing exact positions of various
	fields how would TLB entries be updated from pdir entries in
	memory ?

	Other interesting point to note is that PA-RISC does not
	define how many entries in the table etc. Very much unlike
	x86.

-pkd
	

Re: [hppa-linux] Qn on PA-RISC Page tables and TLB

[Bjorn Helgaas]

>	Exact form of these tables is s/w convention. 
>
>Q.	If the format is software convention, does that mean
>	the fields within TLB slots are not defined by Hardware ?

There is no architectural definition of hardware TLB miss handling,
and most PA-RISC processors do not implement it.

On the ones that do support hardware TLB miss handling, the hardware
expects a certain format, and it is essentially the one given in the
examples in the architecture books.  The hardware TLB walker expects
a hash table of PDIR entries (indexed by a function of the space and
offset), and it only looks at the entries in the table.  Hash collisions
are resolved by a linked list, and the hardware does not walk the list;
this is left for the software miss handler.

Re: [hppa-linux] Qn on PA-RISC Page tables and TLB

[Grant Grundler]

Kumar wrote:
...
> 	Other interesting point to note is that PA-RISC does not
> 	define how many entries in the table etc. Very much unlike
> 	x86.

The CPU pdir can vary in size. For a HW walker, it must be allocated
in physically configuous memory, this pretty much fixes the size
once it's setup.

The size of the CPU PDIR is determined mostly by memory size, amount
of I/O space required (Legacy PA requires memory mapped I/O), and
some fudge factor. Sizing it to allow a HW walker find all physical
mappings is good for performance. I assume this also helps SW TLB
handlers by reducing hash collisions. However, I'm not the expert
on CPU pdir.

K, C-class, and T600 also have an I/O pdir. This is only useful for
systems with more than 4GB (3.75GB?) of physical memory since PA
(and current PCI devices) can only use 32-bits of addressing.
The I/O pdir size depends on how much I/O one wants to allow mapped
at any given time and it too must be physically contigous.
16/th to 8th of physical memory seems to be a pretty good rule of thumb.

For now, I would say ignore the I/O pdir until hppa-linux has a
login prompt. If the OS doesn't use the I/O pdir, it just implies
the DMA is not coherent with Processor activity - just like on
an x86 box. I haven't studied Linux I/O subsytem enough to know
where/how to integrate support for an I/O pdir. I hope the HP-UX
docs released help explain this - search for keyword "CDIO".

grant

Re: [hppa-linux] Qn on PA-RISC Page tables and TLB

[Craig Hada]

> 
> 
> PA-RISC Arch 1.1 book says:
> On page 3-14:
> 
> 	Exact form of these tables is s/w convention. 
> 
> Q.	If the format is software convention, does that mean
> 	the fields within TLB slots are not defined by Hardware ?
> 	Though  the book does seem to indicate what fields are needed
> 	in a pdir entry. Without knowing exact positions of various
> 	fields how would TLB entries be updated from pdir entries in
> 	memory ?
> 

In the absense of a harware TLB walker, the page directory format can be
structured by software to fit its needs. However, the TLB miss handler
must reformat the bits to fit the format of the TLB insert instructions.
To get maximum performace from the system, the TLB miss handlers must be
made very efficient. The format of the page directory entry in the PA-RISC 
Arch 1.1 book minimizes the work of the TLB miss handlers by aligning the
fields to match the format of the TLB insert instructions.

In order to enable the hardware TLB walker, the format of the page directory
must match the format from PA-RISC Arch 1.1 book. In addition, the memory
for the page directory must be equivalently mapped, power of two size aligned
(ie a page directory 1 MB in size must start on a 1 MB boundary), and 
contiguous. 

> 	Other interesting point to note is that PA-RISC does not
> 	define how many entries in the table etc. Very much unlike
> 	x86.
> 
> -pkd

The number of entries in the page directory are a function of the amount of 
memory and the amount of memory mapped I/O in the box. Since the hash
function is not perfect, the size of page directory can be tuned to meet
the system requirements.

-Craig
> 	
> 
> 
> 
> 
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Re: [hppa-linux] Qn on PA-RISC Page tables and TLB

[Kumar]

On Thu, 25 Mar 1999, Craig Hada wrote:
> > 
> 
> In the absense of a harware TLB walker, the page directory format can be
> structured by software to fit its needs. However, the TLB miss handler
> must reformat the bits to fit the format of the TLB insert instructions.
> To get maximum performace from the system, the TLB miss handlers must be
> made very efficient. The format of the page directory entry in the PA-RISC 
> Arch 1.1 book minimizes the work of the TLB miss handlers by aligning the
> fields to match the format of the TLB insert instructions.
> > 	
> > 
Is it necessary that the virtual to physical mappings in TLB be inserted
only in a tlb miss fault. Can I insert  entries in the anticipation that
there will be a fault soon, for example when I first enable 
virtual mode ? If not, there is a potential chicken and egg problem
because I will get a TLB miss fault as soon as I turn virtual mode on and
TLB miss fault handler has to run in virtual mode with translations
on.....and there aint any tranlations yet inserted ...you get the pitcure

							-pkd

Re: [hppa-linux] Qn on PA-RISC Page tables and TLB

[Michael Shalayeff]

Making, drinking tea and reading an opus magnum from Kumar:
> 
> On Thu, 25 Mar 1999, Craig Hada wrote:
> > > 
> > 
> > In the absense of a harware TLB walker, the page directory format can be
> > structured by software to fit its needs. However, the TLB miss handler
> > must reformat the bits to fit the format of the TLB insert instructions.
> > To get maximum performace from the system, the TLB miss handlers must be
> > made very efficient. The format of the page directory entry in the PA-RISC 
> > Arch 1.1 book minimizes the work of the TLB miss handlers by aligning the
> > fields to match the format of the TLB insert instructions.
> > > 	
> > > 
> Is it necessary that the virtual to physical mappings in TLB be inserted
> only in a tlb miss fault. Can I insert  entries in the anticipation that
> there will be a fault soon, for example when I first enable 
> virtual mode ? If not, there is a potential chicken and egg problem
> because I will get a TLB miss fault as soon as I turn virtual mode on and
> TLB miss fault handler has to run in virtual mode with translations
> on.....and there aint any tranlations yet inserted ...you get the pitcure
usually kernel (and tlb miss handler) get block-mapped w/ block tlb,
so the whole kernel text+data get mapped once w/ one big tlb entry,
and won't get no tlb misses for it no more.
so, the chicken gonna be ok.

cu

-- 
    paranoic mickey       (my employers have changed but, the name has remained)

Re: [hppa-linux] Qn on PA-RISC Page tables and TLB

[Craig Hada]

> 
> On Thu, 25 Mar 1999, Craig Hada wrote:
> > > 
> > 
> > In the absense of a harware TLB walker, the page directory format can be
> > structured by software to fit its needs. However, the TLB miss handler
> > must reformat the bits to fit the format of the TLB insert instructions.
> > To get maximum performace from the system, the TLB miss handlers must be
> > made very efficient. The format of the page directory entry in the PA-RISC 
> > Arch 1.1 book minimizes the work of the TLB miss handlers by aligning the
> > fields to match the format of the TLB insert instructions.
> > > 	
> > > 
> Is it necessary that the virtual to physical mappings in TLB be inserted
> only in a tlb miss fault. Can I insert  entries in the anticipation that
> there will be a fault soon, for example when I first enable 
> virtual mode ? If not, there is a potential chicken and egg problem
> because I will get a TLB miss fault as soon as I turn virtual mode on and
> TLB miss fault handler has to run in virtual mode with translations
> on.....and there aint any tranlations yet inserted ...you get the pitcure
> 
> 							-pkd
> 
> 
Under HP-UX, the TLB miss handler runs in real mode (data and code translation
disabled) so there is no need to have a virtual translation for the code 
representing the TLB miss handler or the page directory (both are equivalently
mapped). If a translation is not found in the page directory, then you enter
virtual mode to handle the page fault.

You can speculatively insert entries into the TLB but you also may be
replacing entries that are soon to be used. Since the TLB replacement 
algorithm is not documented, you are probably better off just inserting
the missed upon translation.

-Craig 

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