Linux PCI subsystem development
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From: Shawn Lin <shawn.lin@rock-chips.com>
To: Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org, Shawn Lin <shawn.lin@rock-chips.com>
Subject: [PATCH v2] PCI: Add ASPM quirk for Hi1105 PCIe Wi-Fi
Date: Wed, 12 Nov 2025 10:58:39 +0800	[thread overview]
Message-ID: <1762916319-139532-1-git-send-email-shawn.lin@rock-chips.com> (raw)

This Wi-Fi advertises the L0s and L1 capabilities but actually
it doesn't support them. This's comfirmed by Hisilicon team in
actual productization.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---

Changes in v2:
- rebase on linux-next
- use DECLARE_PCI_FIXUP_HEADER(Bjorn)

 drivers/pci/quirks.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 44e7807..24c2788 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2536,6 +2536,7 @@ static void quirk_disable_aspm_l0s_l1_cap(struct pci_dev *dev)
 	pci_info(dev, "ASPM: L0s L1 removed from Link Capabilities to work around device defect\n");
 }
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1_cap);
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1_cap);
 
 /*
  * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain
-- 
2.7.4


             reply	other threads:[~2025-11-12  2:58 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-11-12  2:58 Shawn Lin [this message]
2025-11-13  0:59 ` [PATCH v2] PCI: Add ASPM quirk for Hi1105 PCIe Wi-Fi Bjorn Helgaas
2025-11-13  1:47   ` Shawn Lin
2025-11-13 12:19     ` Bjorn Helgaas

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