From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <andersson@kernel.org>,
"Konrad Dybcio" <konrad.dybcio@somainline.org>,
"Rob Herring" <robh+dt@kernel.org>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@ti.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
Johan Hovold <johan@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org
Subject: [PATCH v3 4/9] phy: qcom-qmp-pcie: split PHY programming to separate functions
Date: Fri, 9 Sep 2022 12:14:28 +0300 [thread overview]
Message-ID: <20220909091433.3715981-5-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220909091433.3715981-1-dmitry.baryshkov@linaro.org>
Split the code using PHY programming tables into separate functions,
which take a single struct qmp_phy_cfg_tables instance.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 92 +++++++++++++-----------
1 file changed, 49 insertions(+), 43 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index ca8dffaf1081..5250c3f06c89 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -1949,15 +1949,54 @@ static void qcom_qmp_phy_pcie_configure(void __iomem *base,
qcom_qmp_phy_pcie_configure_lane(base, regs, tbl, num, 0xff);
}
-static int qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy)
+static void qcom_qmp_phy_pcie_serdes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables)
{
const struct qmp_phy_cfg *cfg = qphy->cfg;
void __iomem *serdes = qphy->serdes;
- qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->main.serdes_tbl, cfg->main.serdes_tbl_num);
- qcom_qmp_phy_pcie_configure(serdes, cfg->regs, cfg->secondary.serdes_tbl, cfg->secondary.serdes_tbl_num);
+ if (!tables)
+ return;
- return 0;
+ qcom_qmp_phy_pcie_configure(serdes, cfg->regs, tables->serdes_tbl, tables->serdes_tbl_num);
+}
+
+static void qcom_qmp_phy_pcie_lanes_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables)
+{
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *tx = qphy->tx;
+ void __iomem *rx = qphy->rx;
+
+ if (!tables)
+ return;
+
+ qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs,
+ tables->tx_tbl, tables->tx_tbl_num, 1);
+
+ if (cfg->is_dual_lane_phy)
+ qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs,
+ tables->tx_tbl, tables->tx_tbl_num, 2);
+
+ qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs,
+ tables->rx_tbl, tables->rx_tbl_num, 1);
+ if (cfg->is_dual_lane_phy)
+ qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs,
+ tables->rx_tbl, tables->rx_tbl_num, 2);
+}
+
+static void qcom_qmp_phy_pcie_pcs_init(struct qmp_phy *qphy, const struct qmp_phy_cfg_tables *tables)
+{
+ const struct qmp_phy_cfg *cfg = qphy->cfg;
+ void __iomem *pcs = qphy->pcs;
+ void __iomem *pcs_misc = qphy->pcs_misc;
+
+ if (!tables)
+ return;
+
+ qcom_qmp_phy_pcie_configure(pcs, cfg->regs,
+ tables->pcs_tbl, tables->pcs_tbl_num);
+ qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs,
+ tables->pcs_misc_tbl,
+ tables->pcs_misc_tbl_num);
}
static int qcom_qmp_phy_pcie_com_init(struct qmp_phy *qphy)
@@ -2041,15 +2080,13 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
struct qmp_phy *qphy = phy_get_drvdata(phy);
struct qcom_qmp *qmp = qphy->qmp;
const struct qmp_phy_cfg *cfg = qphy->cfg;
- void __iomem *tx = qphy->tx;
- void __iomem *rx = qphy->rx;
void __iomem *pcs = qphy->pcs;
- void __iomem *pcs_misc = qphy->pcs_misc;
void __iomem *status;
unsigned int mask, val, ready;
int ret;
- qcom_qmp_phy_pcie_serdes_init(qphy);
+ qcom_qmp_phy_pcie_serdes_init(qphy, &cfg->main);
+ qcom_qmp_phy_pcie_serdes_init(qphy, &cfg->secondary);
ret = clk_prepare_enable(qphy->pipe_clk);
if (ret) {
@@ -2058,42 +2095,11 @@ static int qcom_qmp_phy_pcie_power_on(struct phy *phy)
}
/* Tx, Rx, and PCS configurations */
- qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs,
- cfg->main.tx_tbl, cfg->main.tx_tbl_num, 1);
- qcom_qmp_phy_pcie_configure_lane(tx, cfg->regs,
- cfg->secondary.tx_tbl, cfg->secondary.tx_tbl_num, 1);
+ qcom_qmp_phy_pcie_lanes_init(qphy, &cfg->main);
+ qcom_qmp_phy_pcie_lanes_init(qphy, &cfg->secondary);
- /* Configuration for other LANE for USB-DP combo PHY */
- if (cfg->is_dual_lane_phy) {
- qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs,
- cfg->main.tx_tbl, cfg->main.tx_tbl_num, 2);
- qcom_qmp_phy_pcie_configure_lane(qphy->tx2, cfg->regs,
- cfg->secondary.tx_tbl, cfg->secondary.tx_tbl_num, 2);
- }
-
- qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs,
- cfg->main.rx_tbl, cfg->main.rx_tbl_num, 1);
- qcom_qmp_phy_pcie_configure_lane(rx, cfg->regs,
- cfg->secondary.rx_tbl, cfg->secondary.rx_tbl_num, 1);
-
- if (cfg->is_dual_lane_phy) {
- qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs,
- cfg->main.rx_tbl, cfg->main.rx_tbl_num, 2);
- qcom_qmp_phy_pcie_configure_lane(qphy->rx2, cfg->regs,
- cfg->secondary.rx_tbl, cfg->secondary.rx_tbl_num, 2);
- }
-
- qcom_qmp_phy_pcie_configure(pcs, cfg->regs,
- cfg->main.pcs_tbl, cfg->main.pcs_tbl_num);
- qcom_qmp_phy_pcie_configure(pcs, cfg->regs,
- cfg->secondary.pcs_tbl, cfg->secondary.pcs_tbl_num);
-
- qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs,
- cfg->main.pcs_misc_tbl,
- cfg->main.pcs_misc_tbl_num);
- qcom_qmp_phy_pcie_configure(pcs_misc, cfg->regs,
- cfg->secondary.pcs_misc_tbl,
- cfg->secondary.pcs_misc_tbl_num);
+ qcom_qmp_phy_pcie_pcs_init(qphy, &cfg->main);
+ qcom_qmp_phy_pcie_pcs_init(qphy, &cfg->secondary);
/*
* Pull out PHY from POWER DOWN state.
--
2.35.1
next prev parent reply other threads:[~2022-09-09 9:14 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-09 9:14 [PATCH v3 0/9] PCI: qcom: Support using the same PHY for both RC and EP Dmitry Baryshkov
2022-09-09 9:14 ` [PATCH v3 1/9] phy: define submodes for PCIe PHYs Dmitry Baryshkov
2022-09-24 6:18 ` Vinod Koul
2022-09-09 9:14 ` [PATCH v3 2/9] phy: qcom-qmp-pcie: drop if (table) conditions Dmitry Baryshkov
2022-09-09 9:14 ` [PATCH v3 3/9] phy: qcom-qmp-pcie: split register tables into main and secondary parts Dmitry Baryshkov
2022-09-09 9:14 ` Dmitry Baryshkov [this message]
2022-09-09 9:14 ` [PATCH v3 5/9] phy: qcom-qmp-pcie: turn secondary programming table into a pointer Dmitry Baryshkov
2022-09-14 6:59 ` Johan Hovold
2022-09-09 9:14 ` [PATCH v3 6/9] phy: qcom-qmp-pcie: support separate tables for EP mode Dmitry Baryshkov
2022-09-09 9:14 ` [PATCH v3 7/9] phy: qcom-qmp-pcie: Support SM8450 PCIe1 PHY in " Dmitry Baryshkov
2022-09-09 9:14 ` [PATCH v3 8/9] PCI: qcom: Setup PHY to work in RC mode Dmitry Baryshkov
2022-09-09 9:14 ` [PATCH v3 9/9] PCI: qcom-ep: Setup PHY to work in EP mode Dmitry Baryshkov
2022-09-14 6:48 ` [PATCH v3 0/9] PCI: qcom: Support using the same PHY for both RC and EP Johan Hovold
2022-09-24 5:48 ` Vinod Koul
2022-09-26 7:09 ` Johan Hovold
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220909091433.3715981-5-dmitry.baryshkov@linaro.org \
--to=dmitry.baryshkov@linaro.org \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=bhelgaas@google.com \
--cc=gustavo.pimentel@synopsys.com \
--cc=jingoohan1@gmail.com \
--cc=johan@kernel.org \
--cc=kishon@ti.com \
--cc=konrad.dybcio@somainline.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=p.zabel@pengutronix.de \
--cc=robh+dt@kernel.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox