From: Matt Ranostay <mranostay@ti.com>
To: <robh@kernel.org>, <tjoseph@cadence.com>, <nm@ti.com>,
<a-verma1@ti.com>, <vigneshr@ti.com>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-pci@vger.kernel.org>, Matt Ranostay <mranostay@ti.com>
Subject: [PATCH v3 0/3] PCI: add 4x lane support for pci-j721e controllers
Date: Wed, 19 Oct 2022 18:29:08 -0700 [thread overview]
Message-ID: <20221020012911.305139-1-mranostay@ti.com> (raw)
Adding of dditional support to Cadence PCIe controller (i.e. pci-j721e.c)
for up to 4x lanes, and reworking of driver to define maximum lanes per
board configuration.
Changes from v1:
* Reworked 'PCI: j721e: Add PCIe 4x lane selection support' to not cause
regressions on 1-2x lane platforms
Changes from v2:
* Correct dev_warn format string from %d to %u since lane count is a unsigned
integer
* Update CC list
Matt Ranostay (3):
PCI: j721e: Add PCIe 4x lane selection support
PCI: j721e: Add per platform maximum lane settings
PCI: j721e: Add warnings on num-lanes misconfiguration
drivers/pci/controller/cadence/pci-j721e.c | 27 ++++++++++++++++++----
1 file changed, 22 insertions(+), 5 deletions(-)
--
2.38.GIT
next reply other threads:[~2022-10-20 2:30 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 1:29 Matt Ranostay [this message]
2022-10-20 1:29 ` [PATCH v3 1/3] PCI: j721e: Add PCIe 4x lane selection support Matt Ranostay
2022-10-25 11:53 ` Vignesh Raghavendra
2022-10-25 12:51 ` Matt Ranostay
2022-10-20 1:29 ` [PATCH v3 2/3] PCI: j721e: Add per platform maximum lane settings Matt Ranostay
2022-10-20 1:29 ` [PATCH v3 3/3] PCI: j721e: Add warnings on num-lanes misconfiguration Matt Ranostay
2022-10-20 16:58 ` Bjorn Helgaas
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