From: Bjorn Helgaas <helgaas@kernel.org>
To: Matthew W Carlis <mattc@purestorage.com>
Cc: sathyanarayanan.kuppuswamy@linux.intel.com, bhelgaas@google.com,
kbusch@kernel.org, linux-pci@vger.kernel.org, lukas@wunner.de,
mika.westerberg@linux.intel.com
Subject: Re: [PATCH 1/1] PCI/portdrv: Allow DPC if the OS controls AER natively.
Date: Mon, 22 Jan 2024 13:32:47 -0600 [thread overview]
Message-ID: <20240122193247.GA278696@bhelgaas> (raw)
In-Reply-To: <20240109001508.32359-1-mattc@purestorage.com>
On Mon, Jan 08, 2024 at 05:15:08PM -0700, Matthew W Carlis wrote:
> A small part is probably historical; we've been using DPC on PCIe
> switches since before there was any EDR support in the kernel. It
> looks like there was a PCIe DPC ECN as early as Feb 2012, but this
> EDR/DPC fw ECN didn't come in till Jan 2019 & kernel support for ECN
> was even later. Its not immediately clear I would want to use EDR in
> my newer architecures & then there are also the older architecures
> still requiring support. When I submitted this patch I came at it
> with the approach of trying to keep the old behavior & still support
> the newer EDR behavior. Bjorns patch from Dec 28 2023 would seem to
> change the behavior for both root ports & switch ports, requiring
> them to set _OSC Control Field bit 7 (DPC) and _OSC Support Field
> bit 7 (EDR) or a kernel command line value. I think no matter what,
> we want to ensure that PCIe Root Ports and PCIe switches arrive at
> the same policy here.
Is there an approved DPC ECN to the PCI Firmware spec that adds DPC
control negotiation, but does *not* add the EDR requirement?
I'm looking at
https://members.pcisig.com/wg/PCI-SIG/document/previewpdf/12888, which
seems to be the final "Downstream Port Containment Related
Enhancements" ECN, which is dated 1/28/2019 and applies to the PCI
Firmware spec r3.2.
It adds bit 7, "PCI Express Downstream Port Containment Configuration
control", to the passed-in _OSC Control field, which indicates that
the OS supports both "native OS control and firmware ownership models
(i.e. Error Disconnect Recover notification) of Downstream Port
Containment."
It also adds the dependency that "If the OS sets bit 7 of the Control
field, it must set bit 7 of the Support field, indicating support for
the Error Disconnect Recover event."
So I'm trying to figure out if the "support DPC but not EDR" situation
was ever a valid place to be. Maybe it's a mistake to have separate
CONFIG_PCIE_DPC and CONFIG_PCIE_EDR options.
CONFIG_PCIE_EDR depends on CONFIG_ACPI, so the situation is a little
bit murky on non-ACPI systems that support DPC.
Bjorn
next prev parent reply other threads:[~2024-01-22 19:32 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-23 21:22 [PATCH 1/1] PCI/portdrv: Allow DPC if the OS controls AER natively Matthew W Carlis
2023-12-23 21:22 ` Matthew W Carlis
2023-12-25 17:53 ` kernel test robot
2023-12-25 20:36 ` kernel test robot
2023-12-26 0:02 ` Matthew W Carlis
2023-12-28 21:23 ` Bjorn Helgaas
2024-01-02 15:41 ` Kuppuswamy Sathyanarayanan
2024-01-08 19:46 ` Matthew W Carlis
2024-01-08 19:53 ` Kuppuswamy Sathyanarayanan
2024-01-09 0:15 ` Matthew W Carlis
2024-01-10 16:41 ` Kuppuswamy Sathyanarayanan
2024-01-10 17:13 ` Kuppuswamy Sathyanarayanan
2024-01-10 20:01 ` Matthew W Carlis
2024-01-10 19:59 ` Matthew W Carlis
2024-01-22 19:32 ` Bjorn Helgaas [this message]
2024-01-23 2:37 ` Kuppuswamy Sathyanarayanan
2024-01-23 15:59 ` Bjorn Helgaas
2024-01-23 23:18 ` Matthew W Carlis
2024-01-24 20:29 ` Bjorn Helgaas
2024-02-21 23:11 ` Bjorn Helgaas
2024-02-21 23:33 ` Bjorn Helgaas
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