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From: Jim Quinlan <james.quinlan@broadcom.com>
To: linux-pci@vger.kernel.org,
	Nicolas Saenz Julienne <nsaenz@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Cyril Brulebois <kibi@debian.org>,
	Stanimir Varbanov <svarbanov@suse.de>,
	Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com,
	james.quinlan@broadcom.com
Cc: "Florian Fainelli" <florian.fainelli@broadcom.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
	BCM2711/BCM2835 ARM ARCHITECTURE),
	linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v6 13/13] PCI: brcmstb: Enable 7712 SOCs
Date: Thu, 15 Aug 2024 18:57:26 -0400	[thread overview]
Message-ID: <20240815225731.40276-14-james.quinlan@broadcom.com> (raw)
In-Reply-To: <20240815225731.40276-1-james.quinlan@broadcom.com>

The Broadcom STB 7712 is the sibling chip of the RPi 5 (2712).
It has one PCIe controller with a single port, supports gen2
and one lane only.  The current revision of the chip is "C0"
or "C1".

Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Reviewed-by: Stanimir Varbanov <svarbanov@suse.de>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
 drivers/pci/controller/pcie-brcmstb.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 26e8f544da4c..21e692a57882 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -1203,6 +1203,10 @@ static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie)
 	const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8;
 	u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */
 
+	/* 7712 does not have this (RGR1) timer */
+	if (pcie->soc_base == BCM7712)
+		return;
+
 	/* Each unit in timeout register is 1/216,000,000 seconds */
 	writel(216 * timeout_us, pcie->base + REG_OFFSET);
 }
@@ -1674,6 +1678,13 @@ static const int pcie_offsets_bmips_7425[] = {
 	[PCIE_INTR2_CPU_BASE] = 0x4300,
 };
 
+static const int pcie_offset_bcm7712[] = {
+	[EXT_CFG_INDEX]  = 0x9000,
+	[EXT_CFG_DATA]   = 0x9004,
+	[PCIE_HARD_DEBUG] = 0x4304,
+	[PCIE_INTR2_CPU_BASE] = 0x4400,
+};
+
 static const struct pcie_cfg_data generic_cfg = {
 	.offsets	= pcie_offsets,
 	.soc_base	= GENERIC,
@@ -1739,6 +1750,14 @@ static const struct pcie_cfg_data bcm7216_cfg = {
 	.num_inbound_wins = 3,
 };
 
+static const struct pcie_cfg_data bcm7712_cfg = {
+	.offsets	= pcie_offset_bcm7712,
+	.perst_set	= brcm_pcie_perst_set_7278,
+	.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
+	.soc_base	= BCM7712,
+	.num_inbound_wins = 10,
+};
+
 static const struct of_device_id brcm_pcie_match[] = {
 	{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
 	{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
@@ -1748,6 +1767,7 @@ static const struct of_device_id brcm_pcie_match[] = {
 	{ .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
 	{ .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
 	{ .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
+	{ .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
 	{},
 };
 
-- 
2.17.1


  parent reply	other threads:[~2024-08-15 22:58 UTC|newest]

Thread overview: 60+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-08-15 22:57 [PATCH v6 00/13] PCI: brcnstb: Enable STB 7712 SOC Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 01/13] dt-bindings: PCI: Change brcmstb maintainer and cleanup Jim Quinlan
2024-08-16  6:52   ` Krzysztof Kozlowski
2024-08-16 15:49   ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 02/13] dt-bindings: PCI: Use maxItems for reset controllers Jim Quinlan
2024-08-16  6:52   ` Krzysztof Kozlowski
2024-08-16 15:49   ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 03/13] dt-bindings: PCI: brcmstb: Add 7712 SoC description Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 04/13] PCI: brcmstb: Use common error handling code in brcm_pcie_probe() Jim Quinlan
2024-08-16  7:02   ` Manivannan Sadhasivam
2024-08-16 15:50   ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 05/13] PCI: brcmstb: Use bridge reset if available Jim Quinlan
2024-08-16  7:07   ` Manivannan Sadhasivam
2024-08-16 15:51   ` Florian Fainelli
2024-08-17 17:41   ` Stanimir Varbanov
2024-08-19 18:09     ` Jim Quinlan
2024-08-19 19:39       ` Stanimir Varbanov
2024-08-19 21:49         ` Jim Quinlan
2024-08-20 23:42           ` Stanimir Varbanov
2024-08-21 14:48             ` Jim Quinlan
2024-08-26 10:42               ` Stanimir Varbanov
2024-08-26 14:17                 ` Jim Quinlan
2024-08-27 12:27                   ` Stanimir Varbanov
2024-08-27 15:01                     ` Jim Quinlan
2024-09-01 18:04                       ` Krzysztof Wilczyński
2024-08-19 19:07     ` Florian Fainelli
2024-08-20 23:38       ` Stanimir Varbanov
2024-08-21 14:32         ` Jim Quinlan
2024-09-02 19:18   ` Bjorn Helgaas
2024-09-03 14:26     ` Jim Quinlan
2024-09-03 14:46       ` Krzysztof Wilczyński
2024-09-03 17:17         ` Bjorn Helgaas
2024-09-03 17:27           ` Krzysztof Wilczyński
2024-09-10 17:30       ` Jim Quinlan
2024-09-10 17:59         ` Bjorn Helgaas
2024-09-10 19:08           ` Krzysztof Wilczyński
2024-09-12 18:21           ` Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 06/13] PCI: brcmstb: Use swinit " Jim Quinlan
2024-08-16  7:08   ` Manivannan Sadhasivam
2024-08-16 15:51   ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 07/13] PCI: brcmstb: PCI: brcmstb: Make HARD_DEBUG, INTR2_CPU_BASE offsets SoC-specific Jim Quinlan
2024-09-02 19:46   ` Bjorn Helgaas
2024-09-03 17:45     ` Florian Fainelli
2024-08-15 22:57 ` [PATCH v6 08/13] PCI: brcmstb: Remove two unused constants from driver Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 09/13] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Jim Quinlan
2024-08-15 22:57 ` [PATCH v6 10/13] PCI: brcmstb: Refactor for chips with many regular inbound windows Jim Quinlan
2024-08-16  7:11   ` Manivannan Sadhasivam
2024-08-16 15:57   ` Florian Fainelli
2024-08-17 16:45   ` Stanimir Varbanov
2024-09-02 20:45   ` Bjorn Helgaas
2024-08-15 22:57 ` [PATCH v6 11/13] PCI: brcmstb: Check return value of all reset_control_xxx calls Jim Quinlan
2024-08-16  7:14   ` Manivannan Sadhasivam
2024-08-15 22:57 ` [PATCH v6 12/13] PCI: brcmstb: Change field name from 'type' to 'soc_base' Jim Quinlan
2024-08-16  7:17   ` Manivannan Sadhasivam
2024-08-16 15:51   ` Florian Fainelli
2024-08-15 22:57 ` Jim Quinlan [this message]
2024-08-16  7:18 ` [PATCH v6 00/13] PCI: brcnstb: Enable STB 7712 SOC Manivannan Sadhasivam
2024-08-19 17:44   ` Jim Quinlan
2024-08-19 17:48     ` Florian Fainelli
2024-09-01 18:01 ` Krzysztof Wilczyński

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