[pci:slot-reset 1/1] drivers/pci/controller/dwc/pcie-dw-rockchip.c:721:58: error: use of undeclared identifier 'PCIE_CLIENT_GENERAL_CON'

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git slot-reset
head:   ebf9d2fae99254fc37f49384b769f363e676018d
commit: ebf9d2fae99254fc37f49384b769f363e676018d [1/1] PCI: dw-rockchip: Add support for slot reset on link down event
config: arm64-randconfig-002-20250515 (https://download.01.org/0day-ci/archive/20250515/202505152337.AoKvnBmd-lkp@intel.com/config)
compiler: clang version 21.0.0git (https://github.com/llvm/llvm-project f819f46284f2a79790038e1f6649172789734ae8)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250515/202505152337.AoKvnBmd-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202505152337.AoKvnBmd-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/pci/controller/dwc/pcie-dw-rockchip.c:721:58: error: use of undeclared identifier 'PCIE_CLIENT_GENERAL_CON'
     721 |         rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, PCIE_CLIENT_GENERAL_CON);
         |                                                                 ^
   1 error generated.


vim +/PCIE_CLIENT_GENERAL_CON +721 drivers/pci/controller/dwc/pcie-dw-rockchip.c

   679	
   680	static int rockchip_pcie_rc_reset_slot(struct pci_host_bridge *bridge,
   681					       struct pci_dev *pdev)
   682	{
   683		struct pci_bus *bus = bridge->bus;
   684		struct dw_pcie_rp *pp = bus->sysdata;
   685		struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
   686		struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
   687		struct device *dev = rockchip->pci.dev;
   688		u32 val;
   689		int ret;
   690	
   691		dw_pcie_stop_link(pci);
   692		clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
   693		rockchip_pcie_phy_deinit(rockchip);
   694	
   695		ret = reset_control_assert(rockchip->rst);
   696		if (ret)
   697			return ret;
   698	
   699		ret = rockchip_pcie_phy_init(rockchip);
   700		if (ret)
   701			goto disable_regulator;
   702	
   703		ret = reset_control_deassert(rockchip->rst);
   704		if (ret)
   705			goto deinit_phy;
   706	
   707		ret = rockchip_pcie_clk_init(rockchip);
   708		if (ret)
   709			goto deinit_phy;
   710	
   711		ret = pp->ops->init(pp);
   712		if (ret) {
   713			dev_err(dev, "host init failed: %d\n", ret);
   714			goto deinit_clk;
   715		}
   716	
   717		/* LTSSM enable control mode. */
   718		val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);
   719		rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);
   720	
 > 721		rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_RC_MODE, PCIE_CLIENT_GENERAL_CON);
   722	
   723		ret = dw_pcie_setup_rc(pp);
   724		if (ret) {
   725			dev_err(dev, "failed to setup RC: %d\n", ret);
   726			goto deinit_clk;
   727		}
   728	
   729		/* Unmask DLL up/down indicator and hot reset/link-down reset IRQ. */
   730		val = HIWORD_UPDATE(PCIE_RDLH_LINK_UP_CHGED | PCIE_LINK_REQ_RST_NOT_INT, 0);
   731		rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_INTR_MASK_MISC);
   732	
   733		ret = dw_pcie_start_link(pci);
   734		if (ret)
   735			goto deinit_clk;
   736	
   737		/* Ignore errors, the link may come up later. */
   738		dw_pcie_wait_for_link(pci);
   739		dev_dbg(dev, "slot reset completed\n");
   740		return ret;
   741	
   742	deinit_clk:
   743		clk_bulk_disable_unprepare(rockchip->clk_cnt, rockchip->clks);
   744	deinit_phy:
   745		rockchip_pcie_phy_deinit(rockchip);
   746	disable_regulator:
   747		if (rockchip->vpcie3v3)
   748			regulator_disable(rockchip->vpcie3v3);
   749	
   750		return ret;
   751	}
   752	

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