From: Bjorn Helgaas <helgaas@kernel.org>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>,
Christian Zigotzky <chzigotzky@xenosoft.de>,
FUKAUMI Naoki <naoki@radxa.com>,
linux-rockchip@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms
Date: Tue, 21 Oct 2025 10:36:42 -0500 [thread overview]
Message-ID: <20251021153642.GA1190961@bhelgaas> (raw)
In-Reply-To: <lmkrtyq6uzhzlz5ttvajnmojegrbfgaz3e3kkwej5qar2lkeof@r5gdlvesm6xl>
On Tue, Oct 21, 2025 at 09:31:22AM +0530, Manivannan Sadhasivam wrote:
> On Mon, Oct 20, 2025 at 05:12:07PM -0500, Bjorn Helgaas wrote:
> > From: Bjorn Helgaas <bhelgaas@google.com>
> >
> > f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree
> > platforms") enabled Clock Power Management and L1 Substates, but that
> > caused regressions because these features depend on CLKREQ#, and not all
> > devices and form factors support it.
>
> I believe we haven't concluded that CLKREQ# is the cluprit here. It
> is probably the best bet, but there could be the device specific
> issues as well.
Yes. There might be things in addition to CLKREQ#, but Clock PM and
L1SS definitely can't work without CLKREQ#. I'll try to convey that
somehow.
> > Reported-by: Christian Zigotzky <chzigotzky@xenosoft.de>
> > Link: https://lore.kernel.org/r/db5c95a1-cf3e-46f9-8045-a1b04908051a@xenosoft.de/
>
> Closes?
Yes, makes sense. I didn't use Closes yet because I didn't want to
presume that it actually fixed the issue. Will change if we get
testing results.
> > + /* For devicetree platforms, enable L0s and L1 by default */
> > if (of_have_populated_dt()) {
> > - link->aspm_default = PCIE_LINK_STATE_ASPM_ALL;
> > + if (link->aspm_support & PCIE_LINK_STATE_L0S)
> > + link->aspm_default |= PCIE_LINK_STATE_L0S;
> > + if (link->aspm_support & PCIE_LINK_STATE_L1)
> > + link->aspm_default |= PCIE_LINK_STATE_L1;
>
> Not sure if it is worth setting these states conditionally. Link
> state enablement code should make use of the cached ASPM cap in
> 'link->aspm_capable'.
I wanted to avoid mentioning an ASPM state that is not advertised in
Link Capabilities, even if later code would ignore it.
> > + pci_info(pdev, "ASPM: DT platform, enabling%s%s\n",
>
> I think you added the 'DT platform,' prefix while applying my patch
> earlier. This is somewhat redundant since the print implies that
> the platform is based on devicetree.
I think "DT platform" is probably unnecessary clutter. I'll drop it
next time.
next prev parent reply other threads:[~2025-10-21 15:36 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-20 22:12 [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms Bjorn Helgaas
2025-10-21 4:01 ` Manivannan Sadhasivam
2025-10-21 12:35 ` Manivannan Sadhasivam
2025-10-21 15:39 ` Bjorn Helgaas
2025-10-21 15:36 ` Bjorn Helgaas [this message]
2025-10-22 19:13 ` Bjorn Helgaas
2025-10-23 4:18 ` FUKAUMI Naoki
2025-10-23 4:25 ` [RESEND] " FUKAUMI Naoki
2025-10-23 5:01 ` FUKAUMI Naoki
2025-10-23 9:30 ` Herve Codina
2025-10-23 5:03 ` Manivannan Sadhasivam
2025-10-23 6:12 ` FUKAUMI Naoki
-- strict thread matches above, loose matches on Subject: below --
2025-10-23 18:06 Bjorn Helgaas
2025-10-23 18:25 ` Bjorn Helgaas
2025-10-23 19:59 ` Diederik de Haas
2025-10-23 20:39 ` Bjorn Helgaas
2025-10-24 4:28 ` Christian Zigotzky
2025-10-23 18:27 ` Dragan Simic
2025-10-23 20:37 ` Bjorn Helgaas
2025-10-24 15:12 ` Johan Hovold
2025-10-24 15:20 ` Johan Hovold
2025-10-24 20:39 ` Bjorn Helgaas
2025-10-27 10:00 ` Johan Hovold
2025-10-27 17:12 ` Christian Zigotzky
2025-10-28 23:33 ` Bjorn Helgaas
2025-10-29 5:47 ` Christian Zigotzky
2025-10-29 15:59 ` Bjorn Helgaas
2025-10-29 17:25 ` Bjorn Helgaas
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