From: Bjorn Helgaas <helgaas@kernel.org>
To: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Cc: Christian Zigotzky <chzigotzky@xenosoft.de>,
FUKAUMI Naoki <naoki@radxa.com>,
linux-rockchip@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms
Date: Wed, 22 Oct 2025 14:13:13 -0500 [thread overview]
Message-ID: <20251022191313.GA1265088@bhelgaas> (raw)
In-Reply-To: <20251020221217.1164153-1-helgaas@kernel.org>
Christian, Naoki, any chance you could test this patch on top of
v6.18-rc1 to see whether it resolves the problem you reported?
I'd like to verify that it works before merging it.
On Mon, Oct 20, 2025 at 05:12:07PM -0500, Bjorn Helgaas wrote:
> From: Bjorn Helgaas <bhelgaas@google.com>
>
> f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree
> platforms") enabled Clock Power Management and L1 Substates, but that
> caused regressions because these features depend on CLKREQ#, and not all
> devices and form factors support it.
>
> Enable only ASPM L0s and L1, and only when both ends of the link advertise
> support for them.
>
> Fixes: f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms")
> Reported-by: Christian Zigotzky <chzigotzky@xenosoft.de>
> Link: https://lore.kernel.org/r/db5c95a1-cf3e-46f9-8045-a1b04908051a@xenosoft.de/
> Reported-by: FUKAUMI Naoki <naoki@radxa.com>
> Link: https://lore.kernel.org/r/22594781424C5C98+22cb5d61-19b1-4353-9818-3bb2b311da0b@radxa.com/
> ---
>
> Mani, not sure what you think we should do here. Here's a stab at it as a
> strawman and in case anybody can test it.
>
> Not sure about the message log message. Maybe OK for testing, but might be
> overly verbose ultimately.
>
> ---
> drivers/pci/pcie/aspm.c | 34 +++++++++-------------------------
> 1 file changed, 9 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
> index 7cc8281e7011..dbc74cc85bcb 100644
> --- a/drivers/pci/pcie/aspm.c
> +++ b/drivers/pci/pcie/aspm.c
> @@ -243,8 +243,7 @@ struct pcie_link_state {
> /* Clock PM state */
> u32 clkpm_capable:1; /* Clock PM capable? */
> u32 clkpm_enabled:1; /* Current Clock PM state */
> - u32 clkpm_default:1; /* Default Clock PM state by BIOS or
> - override */
> + u32 clkpm_default:1; /* Default Clock PM state by BIOS */
> u32 clkpm_disable:1; /* Clock PM disabled */
> };
>
> @@ -376,18 +375,6 @@ static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
> pcie_set_clkpm_nocheck(link, enable);
> }
>
> -static void pcie_clkpm_override_default_link_state(struct pcie_link_state *link,
> - int enabled)
> -{
> - struct pci_dev *pdev = link->downstream;
> -
> - /* For devicetree platforms, enable ClockPM by default */
> - if (of_have_populated_dt() && !enabled) {
> - link->clkpm_default = 1;
> - pci_info(pdev, "ASPM: DT platform, enabling ClockPM\n");
> - }
> -}
> -
> static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
> {
> int capable = 1, enabled = 1;
> @@ -410,7 +397,6 @@ static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
> }
> link->clkpm_enabled = enabled;
> link->clkpm_default = enabled;
> - pcie_clkpm_override_default_link_state(link, enabled);
> link->clkpm_capable = capable;
> link->clkpm_disable = blacklist ? 1 : 0;
> }
> @@ -811,19 +797,17 @@ static void pcie_aspm_override_default_link_state(struct pcie_link_state *link)
> struct pci_dev *pdev = link->downstream;
> u32 override;
>
> - /* For devicetree platforms, enable all ASPM states by default */
> + /* For devicetree platforms, enable L0s and L1 by default */
> if (of_have_populated_dt()) {
> - link->aspm_default = PCIE_LINK_STATE_ASPM_ALL;
> + if (link->aspm_support & PCIE_LINK_STATE_L0S)
> + link->aspm_default |= PCIE_LINK_STATE_L0S;
> + if (link->aspm_support & PCIE_LINK_STATE_L1)
> + link->aspm_default |= PCIE_LINK_STATE_L1;
> override = link->aspm_default & ~link->aspm_enabled;
> if (override)
> - pci_info(pdev, "ASPM: DT platform, enabling%s%s%s%s%s%s%s\n",
> - FLAG(override, L0S_UP, " L0s-up"),
> - FLAG(override, L0S_DW, " L0s-dw"),
> - FLAG(override, L1, " L1"),
> - FLAG(override, L1_1, " ASPM-L1.1"),
> - FLAG(override, L1_2, " ASPM-L1.2"),
> - FLAG(override, L1_1_PCIPM, " PCI-PM-L1.1"),
> - FLAG(override, L1_2_PCIPM, " PCI-PM-L1.2"));
> + pci_info(pdev, "ASPM: DT platform, enabling%s%s\n",
> + FLAG(override, L0S, " L0s"),
> + FLAG(override, L1, " L1"));
> }
> }
>
> --
> 2.43.0
>
next prev parent reply other threads:[~2025-10-22 19:13 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-20 22:12 [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms Bjorn Helgaas
2025-10-21 4:01 ` Manivannan Sadhasivam
2025-10-21 12:35 ` Manivannan Sadhasivam
2025-10-21 15:39 ` Bjorn Helgaas
2025-10-21 15:36 ` Bjorn Helgaas
2025-10-22 19:13 ` Bjorn Helgaas [this message]
2025-10-23 4:18 ` FUKAUMI Naoki
2025-10-23 4:25 ` [RESEND] " FUKAUMI Naoki
2025-10-23 5:01 ` FUKAUMI Naoki
2025-10-23 9:30 ` Herve Codina
2025-10-23 5:03 ` Manivannan Sadhasivam
2025-10-23 6:12 ` FUKAUMI Naoki
-- strict thread matches above, loose matches on Subject: below --
2025-10-23 18:06 Bjorn Helgaas
2025-10-23 18:25 ` Bjorn Helgaas
2025-10-23 19:59 ` Diederik de Haas
2025-10-23 20:39 ` Bjorn Helgaas
2025-10-24 4:28 ` Christian Zigotzky
2025-10-23 18:27 ` Dragan Simic
2025-10-23 20:37 ` Bjorn Helgaas
2025-10-24 15:12 ` Johan Hovold
2025-10-24 15:20 ` Johan Hovold
2025-10-24 20:39 ` Bjorn Helgaas
2025-10-27 10:00 ` Johan Hovold
2025-10-27 17:12 ` Christian Zigotzky
2025-10-28 23:33 ` Bjorn Helgaas
2025-10-29 5:47 ` Christian Zigotzky
2025-10-29 15:59 ` Bjorn Helgaas
2025-10-29 17:25 ` Bjorn Helgaas
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