Re: [PATCH] PCI/ASPM: Enable only L0s and L1 for devicetree platforms

[Bjorn Helgaas <helgaas@kernel.org>]

On Tue, Oct 21, 2025 at 06:05:07PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Oct 21, 2025 at 09:31:32AM +0530, Manivannan Sadhasivam wrote:
> > On Mon, Oct 20, 2025 at 05:12:07PM -0500, Bjorn Helgaas wrote:

> > > +		if (link->aspm_support & PCIE_LINK_STATE_L0S)
> > > +			link->aspm_default |= PCIE_LINK_STATE_L0S;
> > > +		if (link->aspm_support & PCIE_LINK_STATE_L1)
> > > +			link->aspm_default |= PCIE_LINK_STATE_L1;
> > 
> > Not sure if it is worth setting these states conditionally. Link
> > state enablement code should make use of the cached ASPM cap in
> > 'link->aspm_capable'.
> 
> I see the point now. Without the check, we falsely claim that the
> ASPM states are getting enabled. But we cannot be sure until the
> register write to LNKCTL happens, which will depend on many factors
> (own device capability, upstream/downstream port capability,...)
> 
> To avoid ambiguity, can we reword the log to something like,
> 
> 	"ASPM: Overridding default states %s%s\n"

I think aspm_support already includes the capabilities from both ends
of the link:

        if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L0S)
                link->aspm_support |= PCIE_LINK_STATE_L0S;

        if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
                link->aspm_support |= PCIE_LINK_STATE_L1;