* [PATCH 2/2] PCI: dw-rockchip: Change get_lttssm() to provide L1ss info
2025-11-25 1:53 [PATCH 1/2] PCI: dwc: Add L1ss context to ltssm_status of debugfs Shawn Lin
@ 2025-11-25 1:53 ` Shawn Lin
2025-12-11 16:29 ` Bjorn Helgaas
2025-12-11 1:41 ` [PATCH 1/2] PCI: dwc: Add L1ss context to ltssm_status of debugfs Shawn Lin
2025-12-11 16:29 ` Bjorn Helgaas
2 siblings, 1 reply; 5+ messages in thread
From: Shawn Lin @ 2025-11-25 1:53 UTC (permalink / raw)
To: Bjorn Helgaas; +Cc: linux-rockchip, Manivannan Sadhasivam, linux-pci, Shawn Lin
This patch renames rockchip_pcie_get_ltssm() to rockchip_pcie_get_ltssm_reg()
and adds rockchip_pcie_get_ltssm() to get_lttssm() callback to in order to
show the proper L1 substates. The PCIE_CLIENT_LTSSM_STATUS[5:0] register returns
the same ltssm layout as enum dw_pcie_ltssm. So we only need to tell L1ss apart
and return the proper value defined in pcie-designware.h.
cat /sys/kernel/debug/dwc_pcie_a40000000.pcie/ltssm_status
L1_2 (0x142)
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
---
drivers/pci/controller/dwc/pcie-dw-rockchip.c | 28 ++++++++++++++++---
1 file changed, 24 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index f8605fe61a41..019d4f4f26a6 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -68,6 +68,11 @@
#define PCIE_CLKREQ_NOT_READY FIELD_PREP_WM16(BIT(0), 0)
#define PCIE_CLKREQ_PULL_DOWN FIELD_PREP_WM16(GENMASK(13, 12), 1)
+/* RASDES TBA infomation */
+#define PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN 0x154
+#define PCIE_CLIENT_CDM_RASDES_TBA_L1_1 BIT(4)
+#define PCIE_CLIENT_CDM_RASDES_TBA_L1_2 BIT(5)
+
/* Hot Reset Control Register */
#define PCIE_CLIENT_HOT_RESET_CTRL 0x180
#define PCIE_LTSSM_APP_DLY2_EN BIT(1)
@@ -181,11 +186,25 @@ static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
return 0;
}
-static u32 rockchip_pcie_get_ltssm(struct rockchip_pcie *rockchip)
+static u32 rockchip_pcie_get_ltssm_reg(struct rockchip_pcie *rockchip)
{
return rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_LTSSM_STATUS);
}
+static enum dw_pcie_ltssm rockchip_pcie_get_ltssm(struct dw_pcie *pci)
+{
+ struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
+ u32 val = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_CDM_RASDES_TBA_INFO_CMN);
+
+ if (val & PCIE_CLIENT_CDM_RASDES_TBA_L1_1)
+ return DW_PCIE_LTSSM_L1_1;
+ else if (val & PCIE_CLIENT_CDM_RASDES_TBA_L1_2)
+ return DW_PCIE_LTSSM_L1_2;
+ else
+ return rockchip_pcie_get_ltssm_reg(rockchip) &
+ PCIE_LTSSM_STATUS_MASK;
+}
+
static void rockchip_pcie_enable_ltssm(struct rockchip_pcie *rockchip)
{
rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_ENABLE_LTSSM,
@@ -201,7 +220,7 @@ static void rockchip_pcie_disable_ltssm(struct rockchip_pcie *rockchip)
static bool rockchip_pcie_link_up(struct dw_pcie *pci)
{
struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
- u32 val = rockchip_pcie_get_ltssm(rockchip);
+ u32 val = rockchip_pcie_get_ltssm_reg(rockchip);
return FIELD_GET(PCIE_LINKUP_MASK, val) == PCIE_LINKUP;
}
@@ -485,6 +504,7 @@ static const struct dw_pcie_ops dw_pcie_ops = {
.link_up = rockchip_pcie_link_up,
.start_link = rockchip_pcie_start_link,
.stop_link = rockchip_pcie_stop_link,
+ .get_ltssm = rockchip_pcie_get_ltssm,
};
static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg)
@@ -499,7 +519,7 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg)
rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg);
- dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));
+ dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm_reg(rockchip));
if (reg & PCIE_RDLH_LINK_UP_CHGED) {
if (rockchip_pcie_link_up(pci)) {
@@ -526,7 +546,7 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg)
rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
dev_dbg(dev, "PCIE_CLIENT_INTR_STATUS_MISC: %#x\n", reg);
- dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm(rockchip));
+ dev_dbg(dev, "LTSSM_STATUS: %#x\n", rockchip_pcie_get_ltssm_reg(rockchip));
if (reg & PCIE_LINK_REQ_RST_NOT_INT) {
dev_dbg(dev, "hot reset or link-down reset\n");
--
2.43.0
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH 1/2] PCI: dwc: Add L1ss context to ltssm_status of debugfs
2025-11-25 1:53 [PATCH 1/2] PCI: dwc: Add L1ss context to ltssm_status of debugfs Shawn Lin
2025-11-25 1:53 ` [PATCH 2/2] PCI: dw-rockchip: Change get_lttssm() to provide L1ss info Shawn Lin
@ 2025-12-11 1:41 ` Shawn Lin
2025-12-11 16:29 ` Bjorn Helgaas
2 siblings, 0 replies; 5+ messages in thread
From: Shawn Lin @ 2025-12-11 1:41 UTC (permalink / raw)
To: Bjorn Helgaas, Manivannan Sadhasivam; +Cc: shawn.lin, linux-rockchip, linux-pci
在 2025/11/25 星期二 9:53, Shawn Lin 写道:
> dwc core couldn't distinguish ltssm status among L1.0, L1.1 and L1.2.
> But the variant driver may implement additional register to tell them
> apart. So this patch adds two pseudo definitions for variant drivers to
> transltae their internal L1 substates for debugfs to show.
>
Gentle ping... :)
> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
> ---
> This patch is based on latest pci controller/dwc branch given that L1ss support
> for Rockchip has been applied.
>
> drivers/pci/controller/dwc/pcie-designware-debugfs.c | 2 ++
> drivers/pci/controller/dwc/pcie-designware.h | 4 ++++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-debugfs.c b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
> index 0fbf86c0b97e..df98fee69892 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-debugfs.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-debugfs.c
> @@ -485,6 +485,8 @@ static const char *ltssm_status_string(enum dw_pcie_ltssm ltssm)
> DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ1);
> DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ2);
> DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_RCVRY_EQ3);
> + DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L1_1);
> + DW_PCIE_LTSSM_NAME(DW_PCIE_LTSSM_L1_2);
> default:
> str = "DW_PCIE_LTSSM_UNKNOWN";
> break;
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index d3dc0cd8e7b5..3f4611882e29 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -380,6 +380,10 @@ enum dw_pcie_ltssm {
> DW_PCIE_LTSSM_RCVRY_EQ2 = 0x22,
> DW_PCIE_LTSSM_RCVRY_EQ3 = 0x23,
>
> + /* Variant drivers provide pseudo L1 substates from get_ltssm()*/
> + DW_PCIE_LTSSM_L1_1 = 0x141,
> + DW_PCIE_LTSSM_L1_2 = 0x142,
> +
> DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF,
> };
>
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH 1/2] PCI: dwc: Add L1ss context to ltssm_status of debugfs
2025-11-25 1:53 [PATCH 1/2] PCI: dwc: Add L1ss context to ltssm_status of debugfs Shawn Lin
2025-11-25 1:53 ` [PATCH 2/2] PCI: dw-rockchip: Change get_lttssm() to provide L1ss info Shawn Lin
2025-12-11 1:41 ` [PATCH 1/2] PCI: dwc: Add L1ss context to ltssm_status of debugfs Shawn Lin
@ 2025-12-11 16:29 ` Bjorn Helgaas
2 siblings, 0 replies; 5+ messages in thread
From: Bjorn Helgaas @ 2025-12-11 16:29 UTC (permalink / raw)
To: Shawn Lin; +Cc: Bjorn Helgaas, linux-rockchip, Manivannan Sadhasivam, linux-pci
On Tue, Nov 25, 2025 at 09:53:51AM +0800, Shawn Lin wrote:
> dwc core couldn't distinguish ltssm status among L1.0, L1.1 and L1.2.
> But the variant driver may implement additional register to tell them
> apart. So this patch adds two pseudo definitions for variant drivers to
> transltae their internal L1 substates for debugfs to show.
s/L1ss/L1 Substates/ in subject
s/ltssm/LTSSM/
s/transltae/translate/
Use imperative mood:
https://chris.beams.io/posts/git-commit/
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/maintainer-tip.rst?id=v6.14#n134
In this case, imperative mood means:
s/So this patch adds/Add/
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -380,6 +380,10 @@ enum dw_pcie_ltssm {
> DW_PCIE_LTSSM_RCVRY_EQ2 = 0x22,
> DW_PCIE_LTSSM_RCVRY_EQ3 = 0x23,
>
> + /* Variant drivers provide pseudo L1 substates from get_ltssm()*/
Add space before "*/".
> + DW_PCIE_LTSSM_L1_1 = 0x141,
> + DW_PCIE_LTSSM_L1_2 = 0x142,
> +
> DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF,
> };
>
> --
> 2.43.0
>
>
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 5+ messages in thread