[PATCH v3 0/2] PCI: tegra194: ASPM L1 entrance latency from device tree

[PATCH v3 0/2] PCI: tegra194: ASPM L1 entrance latency from device tree

[Manikanta Maddireddy]

This series programs Synopsys DesignWare ASPM L1 entrance latency on NVIDIA
Tegra194/234 PCIe controllers from an optional device tree property and
corrects the default nanosecond cells so the PORT_AFR field advertises the
intended latency buckets.

Background
----------
The controller exposes L1 entrance latency in PCI Express PORT_AFR (DW DBI),
bits 27:29.  Software must select a 3-bit code for the maximum L1 entry delay
the platform can tolerate.  Patch 1 reads aspm-l1-entry-delay-ns (nanoseconds),
converts to whole microseconds with ceiling division (DIV_ROUND_UP), and
programs min(order_base_2(us), 7) into PORT_AFR during ASPM init.  If the
property is absent, the driver keeps the existing default (code 7).

PORT_AFR L1 entrance latency encoding (bits 27:29)
--------------------------------------------------
  +--------------------------+----------+
  | Advertised maximum       | Code     |
  +--------------------------+----------+
  | Maximum of 1 us          | 000b     |
  +--------------------------+----------+
  | Maximum of 2 us          | 001b     |
  +--------------------------+----------+
  | Maximum of 4 us          | 010b     |
  +--------------------------+----------+
  | Maximum of 8 us          | 011b     |
  +--------------------------+----------+
  | Maximum of 16 us         | 100b     |
  +--------------------------+----------+
  | Maximum of 32 us         | 101b     |
  +--------------------------+----------+
  | Maximum of 64 us         | 110b     |
  +--------------------------+----------+
  | Rest                     | 111b     |
  +--------------------------+----------+

Patch summary
-------------
 1/2  PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance
      latency

      Add driver support described above.  v1 and v2 could not program
      encoding 0 (000b, 1 us bucket); v3 uses order_base_2(us) so values map
      to the table.

 2/2  arm64: tegra: fix aspm-l1-entry-delay-ns L1 latency cells

      Commit d60ed99f1c9e ("arm64: tegra: Add aspm-l1-entry-delay-ns to PCIe
      nodes") added 4000 / 8000 / 16000 ns cells.  After ceiling conversion
      those are 4 / 8 / 16 us, yielding PORT_AFR codes 2 / 3 / 4.  The
      intended advertisement is codes 3 / 4 / 5 (8 / 16 / 32 us buckets).
      Double each nanosecond cell:

        tegra194.dtsi: 4000 -> 8000 ns (all Root Port and Endpoint nodes)
        tegra234.dtsi: 8000 -> 16000 ns (Root Port), 16000 -> 32000 ns (Endpoint)

      With the v3 driver mapping in place, the original nanosecond cells no
      longer yield the intended PORT_AFR codes; doubling them restores codes
      3 / 4 / 5 as described above.

      Fixes: d60ed99f1c9e ("arm64: tegra: Add aspm-l1-entry-delay-ns to PCIe nodes")

Testing
-------
 - Verified device tree parsing and PORT_AFR encoding on target hardware.
 - Exercised boundary nanosecond values with a temporary debug patch.
 - Built on x86_64 (previous revision exposed a tree build failure).

Manikanta Maddireddy (2):
  PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance
    latency
  arm64: tegra: fix aspm-l1-entry-delay-ns L1 latency cells

 arch/arm64/boot/dts/nvidia/tegra194.dtsi   | 18 ++++++------
 arch/arm64/boot/dts/nvidia/tegra234.dtsi   | 32 +++++++++++-----------
 drivers/pci/controller/dwc/pcie-tegra194.c | 13 +++++++++
 3 files changed, 38 insertions(+), 25 deletions(-)

-- 
2.34.1

[PATCH v3 1/2] PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency

[Manikanta Maddireddy]

Program the Synopsys DesignWare PORT_AFR L1 entrance latency field from the
optional aspm-l1-entry-delay-ns device tree property (nanoseconds).

Convert delay to whole microseconds with ceiling division (DIV_ROUND_UP),
then derive the 3-bit hw encoding as the minimum of order_base_2(us) and 7.
If the property is not present or cannot be read, default to 7.

Hardware encoding (PORT_AFR L1 entrance latency, bits 27:29):

  +--------------------------+----------+
  | Advertised maximum       | Code     |
  +--------------------------+----------+
  | Maximum of 1 us          | 000b     |
  +--------------------------+----------+
  | Maximum of 2 us          | 001b     |
  +--------------------------+----------+
  | Maximum of 4 us          | 010b     |
  +--------------------------+----------+
  | Maximum of 8 us          | 011b     |
  +--------------------------+----------+
  | Maximum of 16 us         | 100b     |
  +--------------------------+----------+
  | Maximum of 32 us         | 101b     |
  +--------------------------+----------+
  | Maximum of 64 us         | 110b     |
  +--------------------------+----------+
  | Rest                     | 111b     |
  +--------------------------+----------+

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
V2: Fixed commit message as per review comments.
V3: Fixed encoding to handle all cases per above table.

 drivers/pci/controller/dwc/pcie-tegra194.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 9dcfa194050e..5309a2f1356d 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -272,6 +272,7 @@ struct tegra_pcie_dw {
 	u32 aspm_cmrt;
 	u32 aspm_pwr_on_t;
 	u32 aspm_l0s_enter_lat;
+	u32 aspm_l1_enter_lat;
 
 	struct regulator *pex_ctl_supply;
 	struct regulator *slot_ctl_3v3;
@@ -715,6 +716,8 @@ static void init_host_aspm(struct tegra_pcie_dw *pcie)
 	val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
 	val &= ~PORT_AFR_L0S_ENTRANCE_LAT_MASK;
 	val |= (pcie->aspm_l0s_enter_lat << PORT_AFR_L0S_ENTRANCE_LAT_SHIFT);
+	val &= ~PORT_AFR_L1_ENTRANCE_LAT_MASK;
+	val |= (pcie->aspm_l1_enter_lat << PORT_AFR_L1_ENTRANCE_LAT_SHIFT);
 	val |= PORT_AFR_ENTER_ASPM;
 	dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
 }
@@ -1115,6 +1118,7 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
 {
 	struct platform_device *pdev = to_platform_device(pcie->dev);
 	struct device_node *np = pcie->dev->of_node;
+	u32 val;
 	int ret;
 
 	pcie->dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
@@ -1141,6 +1145,15 @@ static int tegra_pcie_dw_parse_dt(struct tegra_pcie_dw *pcie)
 		dev_info(pcie->dev,
 			 "Failed to read ASPM L0s Entrance latency: %d\n", ret);
 
+	/* Default to max latency of 7. */
+	pcie->aspm_l1_enter_lat = 7;
+	ret = of_property_read_u32(np, "aspm-l1-entry-delay-ns", &val);
+	if (!ret) {
+		u32 us = DIV_ROUND_UP(val, 1000);
+
+		pcie->aspm_l1_enter_lat = min_t(u32, order_base_2(us), 7);
+	}
+
 	ret = of_property_read_u32(np, "num-lanes", &pcie->num_lanes);
 	if (ret < 0) {
 		dev_err(pcie->dev, "Failed to read num-lanes: %d\n", ret);
-- 
2.34.1

[PATCH v3 2/2] arm64: tegra: fix aspm-l1-entry-delay-ns L1 latency cells

[Manikanta Maddireddy]

The Tegra194 PCIe driver converts aspm-l1-entry-delay-ns to whole ms
with ceiling division, then derives the Synopsys DesignWare PORT_AFR L1
entrance latency encoding as min(order_base_2(us), 7).

The nanosecond values from the Fixes tag below round up to 4, 8, and 16 us,
selecting PORT_AFR L1 entrance latency codes 2, 3, and 4 respectively.
Raise the programmed latency so the PORT_AFR codes are 3 / 4 / 5
(8 / 16 / 32 us buckets) instead of 2 / 3 / 4 (4 / 8 / 16 us).

- tegra194.dtsi: 4000 -> 8000 ns (all listed controllers)
- tegra234.dtsi: 8000 -> 16000 ns (Root Port), 16000 -> 32000 ns (Endpoint)

Fixes: d60ed99f1c9e ("arm64: tegra: Add aspm-l1-entry-delay-ns to PCIe nodes")
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 18 ++++++-------
 arch/arm64/boot/dts/nvidia/tegra234.dtsi | 32 ++++++++++++------------
 2 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 1d659454a6f9..7bbf0e892724 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -2382,7 +2382,7 @@ pcie@14100000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <4000>;
+			aspm-l1-entry-delay-ns = <8000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -2435,7 +2435,7 @@ pcie@14120000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <4000>;
+			aspm-l1-entry-delay-ns = <8000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -2488,7 +2488,7 @@ pcie@14140000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <4000>;
+			aspm-l1-entry-delay-ns = <8000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -2541,7 +2541,7 @@ pcie@14160000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <4000>;
+			aspm-l1-entry-delay-ns = <8000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -2587,7 +2587,7 @@ pcie-ep@14160000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <4000>;
+			aspm-l1-entry-delay-ns = <8000>;
 
 			interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE4R &emc>,
 					<&mc TEGRA194_MEMORY_CLIENT_PCIE4W &emc>;
@@ -2634,7 +2634,7 @@ pcie@14180000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <4000>;
+			aspm-l1-entry-delay-ns = <8000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -2680,7 +2680,7 @@ pcie-ep@14180000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <4000>;
+			aspm-l1-entry-delay-ns = <8000>;
 
 			interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE0R &emc>,
 					<&mc TEGRA194_MEMORY_CLIENT_PCIE0W &emc>;
@@ -2730,7 +2730,7 @@ pcie@141a0000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <4000>;
+			aspm-l1-entry-delay-ns = <8000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -2779,7 +2779,7 @@ pcie-ep@141a0000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <4000>;
+			aspm-l1-entry-delay-ns = <8000>;
 
 			interconnects = <&mc TEGRA194_MEMORY_CLIENT_PCIE5R &emc>,
 					<&mc TEGRA194_MEMORY_CLIENT_PCIE5W &emc>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
index 75bb9a0ad027..8e0c51e496e2 100644
--- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
@@ -4532,7 +4532,7 @@ pcie@140a0000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <8000>;
+			aspm-l1-entry-delay-ns = <16000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -4587,7 +4587,7 @@ pcie@140c0000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <8000>;
+			aspm-l1-entry-delay-ns = <16000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -4642,7 +4642,7 @@ pcie@140e0000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <8000>;
+			aspm-l1-entry-delay-ns = <16000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -4689,7 +4689,7 @@ pcie-ep@140e0000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <16000>;
+			aspm-l1-entry-delay-ns = <32000>;
 
 			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
 					<&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
@@ -4738,7 +4738,7 @@ pcie@14100000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <8000>;
+			aspm-l1-entry-delay-ns = <16000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -4793,7 +4793,7 @@ pcie@14120000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <8000>;
+			aspm-l1-entry-delay-ns = <16000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -4848,7 +4848,7 @@ pcie@14140000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <8000>;
+			aspm-l1-entry-delay-ns = <16000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -4903,7 +4903,7 @@ pcie@14160000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <8000>;
+			aspm-l1-entry-delay-ns = <16000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -4945,7 +4945,7 @@ pcie-ep@14160000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <16000>;
+			aspm-l1-entry-delay-ns = <32000>;
 
 			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
 				      <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
@@ -4992,7 +4992,7 @@ pcie@14180000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <8000>;
+			aspm-l1-entry-delay-ns = <16000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -5047,7 +5047,7 @@ pcie@141a0000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <8000>;
+			aspm-l1-entry-delay-ns = <16000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -5094,7 +5094,7 @@ pcie-ep@141a0000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <16000>;
+			aspm-l1-entry-delay-ns = <32000>;
 
 			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
 					<&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
@@ -5143,7 +5143,7 @@ pcie@141c0000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <8000>;
+			aspm-l1-entry-delay-ns = <16000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -5190,7 +5190,7 @@ pcie-ep@141c0000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <16000>;
+			aspm-l1-entry-delay-ns = <32000>;
 
 			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
 					<&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
@@ -5239,7 +5239,7 @@ pcie@141e0000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <8000>;
+			aspm-l1-entry-delay-ns = <16000>;
 
 			bus-range = <0x0 0xff>;
 
@@ -5286,7 +5286,7 @@ pcie-ep@141e0000 {
 			nvidia,aspm-cmrt-us = <60>;
 			nvidia,aspm-pwr-on-t-us = <20>;
 			nvidia,aspm-l0s-entrance-latency-us = <3>;
-			aspm-l1-entry-delay-ns = <16000>;
+			aspm-l1-entry-delay-ns = <32000>;
 
 			interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
 					<&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
-- 
2.34.1

Re: [PATCH v3 2/2] arm64: tegra: fix aspm-l1-entry-delay-ns L1 latency cells

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Modifying device tree hardware descriptions to work around a mathematical bug in the driver's latency encoding logic.
- [Low] The commit message incorrectly states that the driver converts aspm-l1-entry-delay-ns to 'whole ms'.
--

commit bbff94096c8fb5346fe688ef1d463490a2efe6df
Author: Manikanta Maddireddy <mmaddireddy@nvidia.com>

arm64: tegra: fix aspm-l1-entry-delay-ns L1 latency cells

This commit updates the aspm-l1-entry-delay-ns property in Tegra194 and
Tegra234 device trees to larger values to adjust the L1 entrance latency
codes programmed by the driver.

> The Tegra194 PCIe driver converts aspm-l1-entry-delay-ns to whole ms
> with ceiling division, then derives the Synopsys DesignWare PORT_AFR L1

This isn't a bug, but there's a typo in the commit message. The driver
uses DIV_ROUND_UP(val, 1000) which converts nanoseconds to microseconds,
not milliseconds.

> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> index 1d659454a6f9f..7bbf0e892724d 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
> @@ -2382,7 +2382,7 @@ pcie@14100000 {
>  			nvidia,aspm-cmrt-us = <60>;
>  			nvidia,aspm-pwr-on-t-us = <20>;
>  			nvidia,aspm-l0s-entrance-latency-us = <3>;
> -			aspm-l1-entry-delay-ns = <4000>;
> +			aspm-l1-entry-delay-ns = <8000>;

Does this work around a driver calculation bug by modifying the device tree
hardware descriptions?

Device tree properties are generally expected to accurately describe physical
hardware in an OS-agnostic way. The issue appears to stem from the driver
using order_base_2() to determine the latency bucket. For exact powers of
two, this returns the exact log2 value. For example, order_base_2(4) is 2.
Code 2 maps to the "2 us to <4 us" bucket, which is insufficient for exactly
4 us.

Could the driver's calculation logic be updated to handle boundary conditions
properly, rather than artificially inflating the hardware values in the
device tree files?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260515070753.3852840-1-mmaddireddy@nvidia.com?part=2

Re: [PATCH v3 2/2] arm64: tegra: fix aspm-l1-entry-delay-ns L1 latency cells

[Manikanta Maddireddy]

On 15/05/26 1:15 pm, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [Medium] Modifying device tree hardware descriptions to work around a mathematical bug in the driver's latency encoding logic.
> - [Low] The commit message incorrectly states that the driver converts aspm-l1-entry-delay-ns to 'whole ms'.
> --
> 
> commit bbff94096c8fb5346fe688ef1d463490a2efe6df
> Author: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> 
> arm64: tegra: fix aspm-l1-entry-delay-ns L1 latency cells
> 
> This commit updates the aspm-l1-entry-delay-ns property in Tegra194 and
> Tegra234 device trees to larger values to adjust the L1 entrance latency
> codes programmed by the driver.
> 
>> The Tegra194 PCIe driver converts aspm-l1-entry-delay-ns to whole ms
>> with ceiling division, then derives the Synopsys DesignWare PORT_AFR L1
> 
> This isn't a bug, but there's a typo in the commit message. The driver
> uses DIV_ROUND_UP(val, 1000) which converts nanoseconds to microseconds,
> not milliseconds.
> 
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
>> index 1d659454a6f9f..7bbf0e892724d 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
>> @@ -2382,7 +2382,7 @@ pcie@14100000 {
>>   			nvidia,aspm-cmrt-us = <60>;
>>   			nvidia,aspm-pwr-on-t-us = <20>;
>>   			nvidia,aspm-l0s-entrance-latency-us = <3>;
>> -			aspm-l1-entry-delay-ns = <4000>;
>> +			aspm-l1-entry-delay-ns = <8000>;
> 
> Does this work around a driver calculation bug by modifying the device tree
> hardware descriptions?
> 
> Device tree properties are generally expected to accurately describe physical
> hardware in an OS-agnostic way. The issue appears to stem from the driver
> using order_base_2() to determine the latency bucket. For exact powers of
> two, this returns the exact log2 value. For example, order_base_2(4) is 2.
> Code 2 maps to the "2 us to <4 us" bucket, which is insufficient for exactly
> 4 us.
> 
> Could the driver's calculation logic be updated to handle boundary conditions
> properly, rather than artificially inflating the hardware values in the
> device tree files?
> 

PORT_AFR L1 entrance latency uses the same style of stepped microsecond
buckets as Endpoint L1 Acceptable Latency in the PCIe spec. On our 
platforms, DWC maps a delay in (2 us, 4 us] to encoding 010b (code 2,
"maximum of 4 us" in the driver table). For that rule, order_base_2(us) 
after DIV_ROUND_UP(ns, 1000) selects the correct code (e.g. 4000 ns → 4 
us → 010b).

- Manikanta

-- 
nvpublic