Re: [PATCH v6 4/9] PCI/CXL: Add sibling function coordination for reset

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Incorrect bit indexing when checking the Non-CXL Function Map DVSEC for non-ARI devices.
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commit b310856ad85d3fc081d86a4d5ea3b158b15fce9f
Author: Srirangan Madhavan <smadhavan@nvidia.com>

PCI/CXL: Add sibling function coordination for reset

This commit adds helpers to collect CXL sibling PCI functions affected by a
CXL reset and prepares them by saving and disabling them. It uses the
Non-CXL Function Map DVSEC to filter out non-CXL functions and functions
without CXL.cache or CXL.mem capabilities.

> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 318744695f628..01effbb4e7cd1 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c

[ ... ]

> @@ -1096,3 +1102,204 @@ cxl_reset_flush_cpu_caches(struct cxl_reset_region_context *ctx)

[ ... ]

> +static bool cxl_reset_is_cxl_sibling(struct pci_dev *pdev,
> +				     struct pci_dev *sibling,
> +				     unsigned long *non_cxl_func_map)
> +{
> +	if (sibling == pdev || sibling->bus != pdev->bus)
> +		return false;
> +
> +	if (pci_ari_enabled(pdev->bus))
> +		return !test_bit(sibling->devfn, non_cxl_func_map);
> +
> +	if (PCI_SLOT(sibling->devfn) != PCI_SLOT(pdev->devfn))
> +		return false;
> +
> +	return !test_bit(PCI_FUNC(sibling->devfn) * 32 +
> +			 PCI_SLOT(sibling->devfn), non_cxl_func_map);

[Severity: High]
Does this formula correctly index the Non-CXL Function Map for non-ARI
devices?

For a non-ARI device, the function map typically uses bits 0-7 to represent
functions 0-7. With this formula, a sibling at function 0 and slot 2 will
evaluate to bit 2 (0 * 32 + 2) instead of bit 0.

If bit 2 happens to be set (indicating function 2 is non-CXL), function 0
could be incorrectly identified as a non-CXL function and excluded from the
reset coordination.

Will this cause the skipped function to miss having its state saved and
IOMMU blocked, potentially leading to lost configuration state, unhandled
IOMMU faults, or driver crashes during the reset?

> +}

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Sashiko AI review · https://sashiko.dev/#/patchset/20260528083154.137979-1-smadhavan@nvidia.com?part=4