Linux PCI subsystem development
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From: Junjie Cao <junjie.cao@intel.com>
To: Shrihari E S <shrihari.s@samsung.com>
Cc: jic23@kernel.org, fan.ni@samsung.com, mst@redhat.com,
	marcel.apfelbaum@gmail.com, dave@stgolabs.net,
	arun.george@samsung.com, dongjoo.seo1@samsung.com,
	s.neeraj@samsung.com, vikash.k5@samsung.com, cpgs@samsung.com,
	gost.dev@samsung.com, linux-cxl@vger.kernel.org,
	linux-pci@vger.kernel.org, qemu-devel@nongnu.org
Subject: Re: [RFC V2 02/10] hw/pci: Move 'x-256b-flit' property from cxl_root_port to pcie_root_port.
Date: Sun, 30 Aug 2026 15:20:20 +0800	[thread overview]
Message-ID: <20260830072020.399442-1-junjie.cao@intel.com> (raw)
In-Reply-To: <111374580.41787732102942.JavaMail.epsvc@epcpadp1new>

Hi Shrihari,

On Wed, 26 Aug 2026 11:04:02 +0530, Shrihari E S wrote:
> @@ -152,6 +152,7 @@ static const Property rp_props[] = {
> +    DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true),
>  };

This moves the default=true along with the property, so it now applies
to every derived root port (pcie-root-port, ioh3420, pnv-phb-root-port,
aspeed.pcie-root-port), not just cxl-rp.  On an empty port the LNKSTA2
flit status bit flips at this patch alone -- pcie_cap_fill_slot_lnk()
consumes flitmode, and pcie_sync_bridge_lnk() only overwrites it once a
child is plugged -- so "does not impact any existing behavior" doesn't
cover the derived ports; with patch 6's pcie_cap_fill_lnk() additions
the ports also come up with Flit Mode Supported (Flags bit 15) and
LNKCTL bit 13 guest-writable.  I checked "-device pcie-root-port" and
"-device ioh3420" on q35 with the series applied: the Express Flags
read 0x8142 on both; before the series the property didn't exist on
these devices and bit 15 stayed 0.

That's a guest-visible config space change on non-CXL machines with no
compat handling.  Migration already breaks at this patch -- pc-q35-9.2
at both ends, plain "-device pcie-root-port", a build at the series
base on the source and one at 2/10 on the destination:

  get_pci_config_device: Bad config data: i=0x87 read: 0 device: 4 cmask: ff ...
  load of migration failed: ... '0000:00:03.0/pcie-root-port'

0x87 is the high byte of PCI_EXP_LNKSTA2; with the whole series on the
destination the first mismatch comes earlier, at 0x57, PCI_EXP_FLAGS.
Fresh q35 guests see different hardware too.  Was extending the default
beyond cxl-rp intended?  If yes, it needs hw_compat entries for older
machine types.  If not, defaulting to off here and setting flitmode
in a cxl-rp instance_init would preserve current behaviour for
non-CXL ports: a second DEFINE_PROP in a subclass asserts on the
duplicate name, and instance_init still runs before qdev applies
globals, so -global and hw_compat keep working.

Many thanks,
Junjie

  reply	other threads:[~2026-08-30  7:20 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20260826052014epcas5p11846c6a40fcec4ec4ba441ceb26e5dcc@epcas5p1.samsung.com>
     [not found] ` <20260826053410.1322176-1-shrihari.s@samsung.com>
2026-08-26  5:34   ` [RFC V2 01/10] hw/pci: Refactor flitmode from PCIESlot to PCIEPort Shrihari E S
2026-08-26  5:34   ` [RFC V2 02/10] hw/pci: Move 'x-256b-flit' property from cxl_root_port to pcie_root_port Shrihari E S
2026-08-30  7:20     ` Junjie Cao [this message]
2026-08-26  5:34   ` [RFC V2 03/10] hw/pci: Add SVC capability and UIO properties to PCIe ports Shrihari E S
2026-08-30  7:20     ` Junjie Cao
2026-08-26  5:34   ` [RFC V2 04/10] hw/cxl: Add Streamlined Virtual Channel (SVC) property to CXL ports Shrihari E S
2026-08-26  5:34   ` [RFC V2 05/10] hw/cxl: Wire UIO capability into HDM decoder and DVSEC registers Shrihari E S
2026-08-30  7:21     ` Junjie Cao
2026-08-26  5:34   ` [RFC V2 06/10] hw/pci: Add PCIe Streamlined Virtual Channel (SVC) capability Shrihari E S
2026-08-30  7:21     ` Junjie Cao
2026-08-26  5:34   ` [RFC V2 07/10] hw/pci: hw/cxl: Wire SVC initialization into port realize functions Shrihari E S
2026-08-30  7:22     ` Junjie Cao
2026-08-26  5:34   ` [RFC V2 08/10] hw/pci: Add PCIe Device3 capability support Shrihari E S
2026-08-30  7:22     ` Junjie Cao
2026-08-26  5:34   ` [RFC V2 09/10] hw/cxl: Wire SVC and Dev3 capability to CXL Type 3 device Shrihari E S
2026-08-30  7:23     ` Junjie Cao
2026-08-26  5:34   ` [RFC V2 10/10] cxl: Add documentation for CXL UIO support Shrihari E S
2026-08-30  7:23     ` Junjie Cao
     [not found] <CGME20260826051958epcas5p3db6cf2ef9115168c5d8dcec7bdb9b8c3@epcas5p3.samsung.com>
2026-08-26  5:34 ` [RFC V2 0/9] hw/pci: hw/cxl: Add UIO support in CXL and PCIe stack Shrihari E S
2026-08-30  7:19   ` Junjie Cao

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