Re: [RFC V2 05/10] hw/cxl: Wire UIO capability into HDM decoder and DVSEC registers

[Junjie Cao <junjie.cao@intel.com>]

Hi Shrihari,

On Wed, 26 Aug 2026 11:04:05 +0530, Shrihari E S wrote:
>      ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY,
> +                     UIO_DECODER_COUNT,
> +                     (type == CXL2_TYPE3_DEVICE || type == CXL2_UPSTREAM_PORT
> +                     || type == CXL2_ROOT_PORT) && uio ? decoder_count : 0);

The always-true expression from v1 is a real type test now, but UIO
Capable Decoder Count uses the same encoding as Decoder Count -- CXL
3.2 8.2.4.20.1: "See the Decoder Count field in this register for
enumeration" -- so writing decoder_count raw advertises 4h = 8 UIO
decoders while Decoder Count reads 2h = 4.  I read the register back on
a cxl-rp: 0x00042312, bits[3:0] = 2h but bits[19:16] = 4h.
cxl_decoder_count_enc() would line the two up.  The same field
description also marks it reserved for CXL.mem devices ("not permitted
to limit the number of UIO-capable HDM decoders"), so CXL2_TYPE3_DEVICE
should drop out of the count expression.

On the type list itself: 8.2.4.20.1 enumerates UIO Capable for CXL.mem
devices, USPs and CXL Host Bridges, the Host Bridge case being the one
that means "all the root ports within this Host Bridge are capable of
routing UIO requests".  This sets it per root port instead, and
pci_expander_bridge.c passes uio=false for CXL2_RC unconditionally, so
the host bridge never advertises it.  On v1 I said a root port may well
be intended, going off crp->uio_capable in the SVC wiring, but the
enumeration above doesn't list one.  Is the root port the intended
carrier?

> +        if (uio) {
> +            write_msk[R_CXL_HDM_DECODER0_CTRL + i * hdm_inc] |=
> +                R_CXL_HDM_DECODER0_CTRL_UIO_MASK |
> +                R_CXL_HDM_DECODER0_CTRL_UIG_MASK |
> +                R_CXL_HDM_DECODER0_CTRL_UIW_MASK;
> +        }

The if (uio) block adds UIG and UIW to the write mask for every type,
type3 included.  8.2.4.20.7 makes both "RWL for a switch and a Host
Bridge if the UIO Capable bit ... is set" and then "reserved for
CXL.mem devices."  I wrote 0x00ff0000 to decoder 0's Control register
on an x-uio=on type3 and read it straight back; the same write on a
type3 without x-uio reads back 0.  Gating UIG/UIW on the port types,
and leaving UIO alone, would match the table.

Many thanks,
Junjie