From: sashiko-bot@kernel.org
To: "David Matlack" <dmatlack@google.com>
Cc: linux-pci@vger.kernel.org
Subject: Re: [PATCH 06/15] PCI/ASPM: Save LTR state in the saved capability store
Date: Thu, 24 Sep 2026 18:16:41 +0000 [thread overview]
Message-ID: <20260924181641.948C21F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20260924173501.856380-7-dmatlack@google.com>
> Save and restore the LTR maximum latency registers through the per-device
> saved capability store instead of a private pci_cap_saved_state buffer.
>
> Reserve the DWORD by its configuration space offset during device setup,
> and keep accessing the registers a DWORD at a time because some devices
> only support DWORD access to them.
>
> No functional change intended.
>
> Assisted-by: LLM
> Signed-off-by: David Matlack <dmatlack@google.com>
Sashiko has reviewed this patch and found no issues. It looks great!
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260924173501.856380-1-dmatlack@google.com?part=6
next prev parent reply other threads:[~2026-09-24 18:16 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-24 17:34 [PATCH 00/15] PCI: Index saved capability state by configuration space offset David Matlack
2026-09-24 17:34 ` [PATCH 01/15] PCI/DPC: Allocate the DPC save buffer during device setup David Matlack
2026-09-24 17:44 ` sashiko-bot
2026-09-24 17:34 ` [PATCH 02/15] PCI: Add an offset-indexed store for saved capability registers David Matlack
2026-09-24 17:52 ` sashiko-bot
2026-10-06 18:41 ` Josh Hilke
2026-09-24 17:34 ` [PATCH 03/15] PCI: Lay out struct pci_saved_state by configuration space offset David Matlack
2026-09-24 18:01 ` sashiko-bot
2026-09-24 17:34 ` [PATCH 04/15] PCI: Save PCIe state in the saved capability store David Matlack
2026-09-24 18:08 ` sashiko-bot
2026-09-24 17:34 ` [PATCH 05/15] PCI: Save PCI-X " David Matlack
2026-09-24 18:11 ` sashiko-bot
2026-09-24 17:34 ` [PATCH 06/15] PCI/ASPM: Save LTR " David Matlack
2026-09-24 18:16 ` sashiko-bot [this message]
2026-09-24 17:34 ` [PATCH 07/15] PCI/ASPM: Save L1SS " David Matlack
2026-09-24 18:22 ` sashiko-bot
2026-10-06 18:41 ` Josh Hilke
2026-09-24 17:34 ` [PATCH 08/15] PCI/AER: Save AER " David Matlack
2026-09-24 18:26 ` sashiko-bot
2026-09-24 17:34 ` [PATCH 09/15] PCI/PTM: Save PTM " David Matlack
2026-09-24 18:30 ` sashiko-bot
2026-09-24 17:34 ` [PATCH 10/15] PCI/TPH: Save TPH " David Matlack
2026-09-24 18:36 ` sashiko-bot
2026-09-24 17:34 ` [PATCH 11/15] PCI/DPC: Save DPC " David Matlack
2026-09-24 18:40 ` sashiko-bot
2026-09-24 17:34 ` [PATCH 12/15] PCI/VC: Split the VC Resource Control restore into a helper David Matlack
2026-09-24 18:42 ` sashiko-bot
2026-09-24 17:34 ` [PATCH 13/15] PCI/VC: Save VC state in the saved capability store David Matlack
2026-09-24 18:46 ` sashiko-bot
2026-10-06 18:42 ` Josh Hilke
2026-09-24 17:35 ` [PATCH 14/15] PCI: Save reserved capability registers in a single pass David Matlack
2026-09-24 18:56 ` sashiko-bot
2026-10-06 18:42 ` Josh Hilke
2026-09-24 17:35 ` [PATCH 15/15] PCI: Remove the per-capability save buffers David Matlack
2026-09-24 19:01 ` sashiko-bot
2026-10-06 18:42 ` Josh Hilke
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