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* Re: [PATCH v3] PCI: Skip Target Speed quirk on clamped ports with no link
@ 2026-09-21 14:45 Thomas Stegbauer
  0 siblings, 0 replies; 28+ messages in thread
From: Thomas Stegbauer @ 2026-09-21 14:45 UTC (permalink / raw)
  To: Andreas Wild; +Cc: macro, helgaas, linux, linux-pci, regressions

In-Reply-To: <20260801201244.4421-1-andiwild@gmail.com>
References: <20260801201244.4421-1-andiwild@gmail.com>

Hi,

another data point for the regression from 72780f796468 ("PCI: Always
lift 2.5GT/s restriction in PCIe failed link retraining"), for the case
with a device present, which v3 does not appear to cover.

Hardware: Raspberry Pi 5 (BCM2712, pcie-brcmstb), ASMedia ASM1182e
[1b21:1182] Gen2 packet switch on a dual M.2 carrier, one NVMe SSD
behind each downstream port.

Downstream port 7 (0001:02:07.0) does not train at 5GT/s on this board.
Without the backport (v6.12.75) the quirk clamps it and the link comes
up at Gen1, in use for over a year:

  pci 0001:02:07.0: broken device, retraining non-functional downstream link at 2.5GT/s
  LnkSta:  Speed 2.5GT/s, Width x1, DLActive+
  LnkCtl2: Target Link Speed: 2.5GT/s

With the backport (v6.18.50, also v6.18.39; Raspberry Pi downstream
kernels, pcie-brcmstb identical between both 6.18 versions) the device
is lost:

  [0.518303] pci 0001:02:07.0: broken device, retraining non-functional downstream link at 2.5GT/s
  [0.538795] pci 0001:02:07.0: removing 2.5GT/s downstream link speed restriction
  [1.537936] pci 0001:02:07.0: retraining failed
  LnkSta:  Speed 5GT/s, Width x1, DLActive-, BWMgmt+
  LnkCtl2: Target Link Speed: 5GT/s

Same hardware, firmware and DT; only the kernel differs. Swapping the
SSDs moves the failure with the port, not with the drive.

To be fair, the Gen1 link is marginal: AER on the port shows RxErr
right after clearing, and BadTLP/BadDLLP under load. The replays are
absorbed, though: 8 GiB O_DIRECT read at 222 MB/s, no data errors.

So: the port is not clamped on entry, hence v3's new early return does
not trigger; the first block clamps and the link trains at 2.5GT/s; the
second block then lifts the clamp because LnkCap is 5GT/s; the 5GT/s
retrain fails as the initial training did, and the error path restores
the old 5GT/s target, leaving the link down (and adding ~2 s to boot).

Before 72780f796468 the lift was limited to the ASM2824 with the link
up, which is why this worked. Would it make sense to fall back to the
2.5GT/s clamp when lifting fails, rather than to the original target
speed, at least when the clamp had produced a working link?

Happy to test patches (v6.18.y based on the Raspberry Pi tree is
easiest for me). Downstream report with full logs:
https://github.com/raspberrypi/linux/issues/7635

Thanks,
Thomas S.

p.s. hopefully the mail get properly added, as I hade to add the in-reply and reference to the txt-body of the mail.

^ permalink raw reply	[flat|nested] 28+ messages in thread
[parent not found: <DU2PPFBE35756D171CD64356C8D8DF3C2F8AB922@DU2PPFBE35756D1.EURP189.PROD.OUTLOOK.COM>]
* Re: [PATCH v3] PCI: Skip Target Speed quirk on clamped ports with no link
@ 2026-10-07 14:03 SyncNOW.net - Armando Araujo Filho
  0 siblings, 0 replies; 28+ messages in thread
From: SyncNOW.net - Armando Araujo Filho @ 2026-10-07 14:03 UTC (permalink / raw)
  To: andiwild
  Cc: bhelgaas, blaaaat, edwardmalik95, helgaas, linux-kernel,
	linux-pci, macro, regressions, regressions, restafvalendergelijke

Hi Maciej, Bjorn, all,

Another active-link case for 72780f796468 ("PCI: Always lift 2.5GT/s
restriction in PCIe failed link retraining"). It answers two open
questions in this thread:

  - Maciej asked for HASD results. On this port HASD is clear
    (SpeedDis-), so the HASD check Andreas proposed would not help here.
  - This case never reaches the error path (no "retraining failed"),
    so falling back to 2.5GT/s on failure, as Thomas suggested, would
    not help either.

On a Huawei server the onboard BMC VGA controller, a Gen1-only
endpoint, sits behind a firmware-clamped PCH root port. After the quirk
lifts the clamp, the endpoint is missing from the bus scan, even though
the quirk reports no error and the link is up at 2.5GT/s afterwards.
A rescan finds the device again. Reproduced on Arch Linux 7.2.7. The
Proxmox bisection gives the same 7.0.14-6 -> 7.0.14-7 boundary that
Aoxtj and Mich found.

A note on how this report was produced: I am a network/infrastructure
engineer, not a kernel developer. I noticed the problem (loss of video
on a Proxmox upgrade), ran all the tests on the hardware, and collected
the logs, register dumps and kernel bisection below. The analysis was
done with an AI assistant (Anthropic's Claude): it compared the dmesg
and lspci output between kernels, identified the link-speed quirk and
the relevant commit, suggested the setpci recovery test, and drafted
this report. All data below was captured on the machine and I have
checked it against the raw logs. The interpretation in the "our guess"
paragraph and the suggestions at the end should be read as
hypotheses, not as kernel expertise on my part.

Kernels tested
--------------

Same hardware and configuration throughout:

  Good  Proxmox VE 7.0.2-6, 7.0.12-1, 7.0.14-1, 7.0.14-6
        (7.0.14-6 = Ubuntu-7.0.0-28.28i2, stable 6.18.38 / 7.1.3)
  Bad   Proxmox VE 7.0.14-7, 7.0.14-8
        (7.0.14-7 = Ubuntu-7.0.0-28.28i3, stable 6.18.39 / 7.1.4)
  Bad   Arch Linux 7.2.7-arch1-1 (official 2026.10.01 live ISO)

Hardware
--------

  DMI: Huawei Technologies Co., Ltd. Tecal RH2285 V2-12L/BC11SRSC1,
       BIOS RMISV055 02/02/2013
  CPU: 2x Xeon E5 v2 (Ivy Bridge-EP), PCH C600/X79

  Affected path:
    00:1c.3  Root Port 4  [8086:1d16] (rev b6)  LnkCap 5GT/s x1
             SltCap HotPlug- Surprise- (not hot-plug capable)
      03:00.0  XGI Z11/Z11M VGA [18ca:0027]
               Subsystem Huawei [19e5:2013]     LnkCap 2.5GT/s x1
               (PCIe v1 endpoint, Gen1-only; the BMC's video device)

Register state, good vs. bad
----------------------------

  00:1c.3 (root port)     good (7.0.14-6)     bad (7.0.14-7, 7.2.7)
  LnkCap                  5GT/s x1            5GT/s x1
  LnkCtl2 Target Speed    2.5GT/s (firmware)  5GT/s (lifted)
  LnkCtl2 HASD            SpeedDis-           SpeedDis-
  LnkSta                  2.5GT/s x1          2.5GT/s x1
  03:00.0 enumerated      yes                 NO

The link is up (x1) after the quirk too. It just comes back at
2.5GT/s, the most the endpoint supports.

dmesg, Arch Linux 7.2.7-arch1-1
-------------------------------

  Linux version 7.2.7-arch1-1 (linux@archlinux) ... #1 SMP
PREEMPT_DYNAMIC Mon, 21 Sep 2026
  ...
  [    1.019207] pci 0000:00:1c.0: removing 2.5GT/s downstream link
speed restriction
  [    2.019409] pci 0000:00:1c.0: retraining failed
  [    3.019695] pci 0000:00:1c.2: removing 2.5GT/s downstream link
speed restriction
  [    4.020409] pci 0000:00:1c.2: retraining failed
  [    5.021634] pci 0000:00:1c.3: [8086:1d16] type 01 class 0x060400
PCIe Root Port
  [    5.021666] pci 0000:00:1c.3: PCI bridge to [bus 03]
  [    5.021673] pci 0000:00:1c.3:   bridge window [io  0x3000-0x3fff]
  [    5.021678] pci 0000:00:1c.3:   bridge window [mem 0x94b00000-0x94bfffff]
  [    5.021690] pci 0000:00:1c.3:   bridge window [mem
0x90000000-0x93ffffff 64bit pref]
  [    5.021718] pci 0000:00:1c.3: removing 2.5GT/s downstream link
speed restriction
  [    5.021770] pci 0000:00:1c.3: PME# supported from D0 D3hot D3cold
  ...
  [    5.045412] pci 0000:00:1c.3: PCI bridge to [bus 03]
  [    5.076827] vgaarb: loaded                       <- no VGA device

00:1c.0 and 00:1c.2 are empty ports, the case v3 covers.

On the good kernels the same scan finds the endpoint right away:

  pci 0000:03:00.0: [18ca:0027] type 00 class 0x030000 PCIe Endpoint
  pci 0000:03:00.0: BAR 0 [mem 0x90000000-0x93ffffff pref]
  pci 0000:03:00.0: Video device with shadowed ROM at [mem
0x000c0000-0x000dffff]
  pci 0000:03:00.0: vgaarb: setting as boot VGA device

How this differs from the other active-link reports
---------------------------------------------------

In Aoxtj's, Mich's and Thomas's cases the retrain fails, the error
path runs, and the link is left down (x0 / DLLLA=0). Here:

  - there is no "retraining failed" message; the quirk returns about
    50 us after "removing 2.5GT/s ...";
  - the link is up afterwards (2.5GT/s x1);
  - the endpoint is healthy and comes back with a rescan (below).

So the device is only missing because bus 03 is scanned too early.

Our guess, not verified: the retrain takes the link down and back up
(the endpoint cannot do 5GT/s and falls back to 2.5GT/s). The wait in
the quirk may see DLLLA still set from before the link went down and
return at once. The bus below is then scanned while the link is still
retraining, and nothing answers. That would fit the 50 us return and
the missing error message. A one-line pci_info() of LNKSTA right after
pcie_set_target_speed() would show whether this is right. I can run
that, or Andreas's earlier diagnostic, if useful.

Recovery at runtime
-------------------

Restoring the firmware clamp, retraining and rescanning brings the
device back:

  # setpci -s 00:1c.3 CAP_EXP+0x30.w=0001:000f   # LnkCtl2 TLS = 2.5GT/s
  # setpci -s 00:1c.3 CAP_EXP+0x10.w=0020:0020   # LnkCtl Retrain Link
  # sleep 1
  # echo 1 > /sys/bus/pci/rescan

  pci 0000:03:00.0: [18ca:0027] type 00 class 0x030000 PCIe Endpoint
  pci 0000:03:00.0: vgaarb: VGA device added:
decodes=io+mem,owns=none,locks=none
  pcieport 0000:00:1c.3: ASPM: current common clock configuration is
inconsistent, reconfiguring
  pci 0000:03:00.0: BAR 0 [mem 0x90000000-0x93ffffff pref]: assigned
  pci 0000:03:00.0: BAR 1 [mem 0x94200000-0x9423ffff]: assigned
  pci 0000:03:00.0: BAR 2 [io  0x3000-0x307f]: assigned

By then the boot VGA console is already lost, so this only shows that
the device is still there.

Observations
------------

1. HASD is clear on this port, so a HASD-based check would not catch
   this case.

2. The failure is not in the error path, so a 2.5GT/s fallback on
   failure would not help either.

3. The retrain gains nothing here: the endpoint only supports 2.5GT/s
   and the link comes back at that speed. I realise the endpoint is
   not enumerated yet when the quirk runs on the port, so knowing its
   speed in advance may not be simple.

4. If an active link is retrained, waiting for it to actually go down
   and come back (or for the device to become ready) before the bus
   below is scanned might prevent the device going missing.

5. Like Mich's Dell and HP machines, this is an older Intel server
   platform where firmware clamps the ports on purpose. A command-line
   opt-out would give users of such machines a workaround other than
   staying on an older kernel.

I can test patches on this machine with a mainline or live kernel and
can provide full dmesg and lspci -vvv from good and bad kernels.

Thanks,
Armando Araujo Filho

^ permalink raw reply	[flat|nested] 28+ messages in thread
* Re: [PATCH v3] PCI: Skip Target Speed quirk on clamped ports with no link
@ 2026-09-20  8:15 blaat windows
  0 siblings, 0 replies; 28+ messages in thread
From: blaat windows @ 2026-09-20  8:15 UTC (permalink / raw)
  To: linux-pci@vger.kernel.org
  Cc: linux-kernel@vger.kernel.org, regressions@lists.linux.dev

Another reproducible case of the active-link failure described in this thread.

Hardware:
Intel 4th-gen/9-series platform
Intel 82571EB quad-port NIC
Microsemi/PMC/IDT PES12N3A PCIe switch
Root port 00:1c.4, LnkCap 5GT/s x4
Working negotiated link: 2.5GT/s x4

Kernel results:
7.2-rc1 fail
7.1-rc7 succes

On failing kernels, the PES12N3A hierarchy does not enumerate and all four downstream 82571EB ports disappear.

I traced this to pcie_failed_link_retrain() and specifically the new generic clamp-removal code introduced by 72780f7964684939d7d2f69c348876213b184484 ("PCI: Always lift 2.5GT/s restriction in PCIe failed link retraining").

I tested 7.3.0-rc3+ with only this block commented out:

    pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2);
    if ((lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT) {
            pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n");
            ret = pcie_set_target_speed(dev, speed_cap, false);
            if (ret)
                    goto err;
    }

With that block disabled, 7.3.0-rc3+ boots normally, having all four NIC ports enumerate:

07:00.0 82571EB
07:00.1 82571EB
08:00.0 82571EB
08:00.1 82571EB

The important result is that the initial 2.5GT/s recovery is fine. Leaving the link at 2.5GT/s works. It is the subsequent:

    pcie_set_target_speed(dev, speed_cap, false);

which breaks this PES12N3A/82571EB link.

So this appears to be the same active-link failure mode, but with a PES12N3A switch rather than a direct 82571EB connection.

This was tested against vanilla 7.3.0-rc3+ with only the above local change.

I can provide full dmesg/lspci output and test a proposed fix if useful.

^ permalink raw reply	[flat|nested] 28+ messages in thread
* [PATCH v3] PCI: Skip Target Speed quirk on clamped ports with no link
@ 2026-08-01 20:11 Andreas Wild
  2026-08-01 20:20 ` sashiko-bot
                   ` (3 more replies)
  0 siblings, 4 replies; 28+ messages in thread
From: Andreas Wild @ 2026-08-01 20:11 UTC (permalink / raw)
  To: linux-pci; +Cc: bhelgaas, macro, linux-kernel, Andreas Wild

From: "Maciej W. Rozycki" <macro@orcam.me.uk>

Since commit 72780f796468 ("PCI: Always lift 2.5GT/s restriction in PCIe
failed link retraining") the Target Speed quirk lifts a firmware-imposed
2.5GT/s restriction on any downstream port, without checking whether the
link is up.  Where nothing is plugged in, the retraining that follows can
never complete, so each attempt costs PCIE_LINK_RETRAIN_TIMEOUT_MS.  The
quirk makes two of them -- the initial one and the restore on the error
path -- adding a fixed 2 s to every boot.

On an MSI PRO Z690-A WIFI DDR4 (Intel 600 Series PCH) with one empty x1
slot, running v7.2-rc5:

 0.541 pci 0000:00:1c.0: removing 2.5GT/s downstream link speed restriction
 1.541 pci 0000:00:1c.0: retraining failed
 2.541 pci 0000:00:1c.2: [8086:7aba] type 01 class 0x060400

Where the Link Speed has already been clamped at 2.5GT/s and no link has
been established there is nothing worth doing, which is what the kerneldoc
for the quirk already describes: the restriction is to be lifted where
firmware arranged it "and the port reports its link already being up".
Bail out early in that case, before either the ASM2824 workaround or the
removal of the restriction is considered.

Ports whose link is up are unaffected, and so is the ASM2824 workaround,
which is reached with the Target Link Speed not clamped.

With this applied the quirk returns without touching the port: both
messages are gone, enumeration proceeds from 0000:00:1c.0 to 0000:00:1c.2
in 1 ms rather than 2 s, and the systemd "kernel" boot phase goes from
3.011 s to 1.036 s.

Fixes: 72780f796468 ("PCI: Always lift 2.5GT/s restriction in PCIe failed link retraining")
Cc: stable@vger.kernel.org
Reported-by: Andreas Wild <andiwild@gmail.com>
Closes: https://lore.kernel.org/lkml/20260801092152.5643-1-andiwild@gmail.com/
Tested-by: Andreas Wild <andiwild@gmail.com>
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Andreas Wild <andiwild@gmail.com>
---
v3:
 - Replaced with Maciej's much simpler approach: bail out of the quirk
   entirely when the Target Link Speed is already clamped at 2.5GT/s and no
   link has been established, rather than programming the speed and skipping
   only the retraining.  One function, no new API, no bwctrl changes.
 - Note this leaves the Target Link Speed clamped on such a port, where v2
   left it at the Port's maximum.  A device hot-plugged there later trains at
   2.5GT/s: pcie_wait_for_link_delay() only calls the quirk when
   pcie_wait_for_link_status() fails, so a link that comes up cleanly at
   2.5GT/s never re-runs it.  Flagging in case that matters; the clamp is
   firmware's, so honouring it on an unoccupied Port seems defensible.
 - v2: https://lore.kernel.org/lkml/20260801105441.6506-1-andiwild@gmail.com/
 - v1: https://lore.kernel.org/lkml/20260801092152.5643-1-andiwild@gmail.com/
 drivers/pci/quirks.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index b09f27f..9e407c4 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -108,7 +108,11 @@ int pcie_failed_link_retrain(struct pci_dev *dev)
 
 	pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
 	pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &oldlnkctl2);
-	if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) {
+	if (lnksta & PCI_EXP_LNKSTA_DLLLA) {
+		;
+	} else if (PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2) == PCIE_SPEED_2_5GT) {
+		return ret;
+	} else if (pcie_lbms_seen(dev, lnksta)) {
 		pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n");
 		ret = pcie_set_target_speed(dev, PCIE_SPEED_2_5GT, false);
 		if (ret)
-- 
2.55.0


^ permalink raw reply related	[flat|nested] 28+ messages in thread

end of thread, other threads:[~2026-10-09 11:36 UTC | newest]

Thread overview: 28+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-09-21 14:45 [PATCH v3] PCI: Skip Target Speed quirk on clamped ports with no link Thomas Stegbauer
     [not found] <DU2PPFBE35756D171CD64356C8D8DF3C2F8AB922@DU2PPFBE35756D1.EURP189.PROD.OUTLOOK.COM>
2026-10-09 11:21 ` M M
2026-10-09 11:36 ` Thomas Lamprecht
  -- strict thread matches above, loose matches on Subject: below --
2026-10-07 14:03 SyncNOW.net - Armando Araujo Filho
2026-09-20  8:15 blaat windows
2026-08-01 20:11 Andreas Wild
2026-08-01 20:20 ` sashiko-bot
2026-08-03  5:39 ` Thorsten Leemhuis
2026-08-03 22:07   ` Maciej W. Rozycki
2026-08-04  5:32     ` Thorsten Leemhuis
2026-08-07 19:59 ` Aoxtj
2026-08-08  6:31   ` Andreas Wild
2026-08-11  3:43     ` Aoxtj
2026-08-11  6:42       ` Andreas Wild
2026-08-24 14:26         ` Thorsten Leemhuis
2026-08-25  7:05           ` Andreas Wild
2026-08-25 10:18             ` Maciej W. Rozycki
2026-09-02 15:48               ` Thorsten Leemhuis
2026-09-07 12:33                 ` Maciej W. Rozycki
2026-09-17 23:33 ` Bjorn Helgaas
2026-09-18  5:39   ` Thorsten Leemhuis
2026-09-18 10:39     ` Maciej W. Rozycki
2026-09-18 11:00       ` Thorsten Leemhuis
2026-09-18 12:18         ` Maciej W. Rozycki
2026-09-18 12:50           ` Thorsten Leemhuis
2026-09-21 10:33       ` Thorsten Leemhuis
2026-09-29  5:45         ` Thorsten Leemhuis
2026-09-29  7:59           ` Andreas Wild

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