[PATCH 0/2] PCI: qcom: Add PCIe support for upcoming Hawi SoC

[PATCH 0/2] PCI: qcom: Add PCIe support for upcoming Hawi SoC

[Matthew Leung]

This series adds PCIe support for the Qualcomm Hawi SoC. The Hawi
platform features two PCIe controllers: one capable of Gen3 x2 operation
and one capable of Gen4 x1 operation. The first patch adds the device
tree bindings documentation for the Hawi PCIe controller, and the second
patch adds driver support by enabling the Hawi compatible string in the
existing qcom PCIe driver.

This series depends on the following prerequisite series:
- [PATCH v3 0/7] clk: qcom: Add initial clock controllers for the
  upcoming Hawi SoC (Change-ID: 20260316-clk-hawi-1ad4cad36d6a:v3)
- [PATCH v4 0/2] interconnect: qcom: Add support for upcoming Hawi SoC
  (Change-ID: 20260311-icc-hawi-d6dc165f8935:v4)

These dependencies add necessary headers for running dt_binding_check
against the binding.

Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
Matthew Leung (2):
      dt-bindings: PCI: qcom: Document the Hawi PCIe Controller
      PCI: qcom: Add support for Hawi

 .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 188 +++++++++++++++++++++
 drivers/pci/controller/dwc/pcie-qcom.c             |   1 +
 2 files changed, 189 insertions(+)
---
base-commit: 4cd074ae20bbcc293bbbce9163abe99d68ae6ae0
change-id: 20260506-hawi-pcie-f61435ca420c
prerequisite-change-id: 20260316-clk-hawi-1ad4cad36d6a:v3
prerequisite-patch-id: c4fbb0620d748d7f1ee675ade5167775bd31c8ac
prerequisite-patch-id: ae5e212518cc333a1a93564cabfc6abd128df664
prerequisite-patch-id: 3c3816e0d595589fc02383f10e48c83a61fdc9d1
prerequisite-patch-id: cbc13fb819d1c1ee77957393f0958f05db8db864
prerequisite-patch-id: 17e2c0cfbbea826fefa1c67d0f5dc2094ab73d76
prerequisite-patch-id: 150dc74750377f4558deab6b179632872bcbb71c
prerequisite-patch-id: 38fe0da5b18610aeb32c7154f9e50187ccaec6a4
prerequisite-change-id: 20260311-icc-hawi-d6dc165f8935:v4
prerequisite-patch-id: a1ff655f0b21d6259b158ad9f99a95bde31257e6
prerequisite-patch-id: db21b6b20451be8475129faece7ef4191d41273c

Best regards,
--  
Matthew Leung <matthew.leung@oss.qualcomm.com>

[PATCH 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[Matthew Leung]

Add a dedicated schema for the PCIe controllers found on the Hawi
platform.

Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
 .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 188 +++++++++++++++++++++
 1 file changed, 188 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
new file mode 100644
index 000000000000..154bc88e5969
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
@@ -0,0 +1,188 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/qcom,hawi-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Hawi PCI Express Root Complex
+
+maintainers:
+  - Bjorn Andersson <andersson@kernel.org>
+  - Manivannan Sadhasivam <mani@kernel.org>
+
+description:
+  Qualcomm Hawi SoC (and compatible) PCIe root complex controller is based on
+  the Synopsys DesignWare PCIe IP.
+
+properties:
+  compatible:
+    const: qcom,hawi-pcie
+
+  reg:
+    minItems: 5
+    maxItems: 6
+
+  reg-names:
+    minItems: 5
+    items:
+      - const: parf # Qualcomm specific registers
+      - const: dbi # DesignWare PCIe registers
+      - const: elbi # External local bus interface registers
+      - const: atu # ATU address space
+      - const: config # PCIe configuration space
+      - const: mhi # MHI registers
+
+  clocks:
+    maxItems: 7
+
+  clock-names:
+    minItems: 6
+    items:
+      - const: aux # Auxiliary clock
+      - const: cfg # Configuration clock
+      - const: bus_master # Master AXI clock
+      - const: bus_slave # Slave AXI clock
+      - const: slave_q2a # Slave Q2A clock
+      - const: noc_aggr # Aggre NoC PCIe AXI clock
+      - const: cnoc_sf_axi # Config NoC PCIe0 AXI clock
+
+  interrupts:
+    minItems: 8
+    maxItems: 9
+
+  interrupt-names:
+    minItems: 8
+    items:
+      - const: msi0
+      - const: msi1
+      - const: msi2
+      - const: msi3
+      - const: msi4
+      - const: msi5
+      - const: msi6
+      - const: msi7
+      - const: global
+
+  resets:
+    minItems: 1
+    maxItems: 2
+
+  reset-names:
+    minItems: 1
+    items:
+      - const: pci # PCIe core reset
+      - const: link_down # PCIe link down reset
+
+required:
+  - power-domains
+  - resets
+  - reset-names
+
+allOf:
+  - $ref: qcom,pcie-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,hawi-gcc.h>
+    #include <dt-bindings/gpio/gpio.h>
+    #include <dt-bindings/interconnect/qcom,icc.h>
+    #include <dt-bindings/interconnect/qcom,hawi-rpmh.h>
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    soc {
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        pcie@1c00000 {
+            compatible = "qcom,hawi-pcie";
+            reg = <0 0x01c00000 0 0x3000>,
+                  <0 0x40000000 0 0xf1d>,
+                  <0 0x40000f20 0 0xa8>,
+                  <0 0x40001000 0 0x1000>,
+                  <0 0x40100000 0 0x100000>;
+            reg-names = "parf", "dbi", "elbi", "atu", "config";
+            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
+                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;
+
+            bus-range = <0x00 0xff>;
+            device_type = "pci";
+            linux,pci-domain = <0>;
+            num-lanes = <2>;
+
+            #address-cells = <3>;
+            #size-cells = <2>;
+
+            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
+                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+                     <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
+                     <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
+            clock-names = "aux",
+                          "cfg",
+                          "bus_master",
+                          "bus_slave",
+                          "slave_q2a",
+                          "noc_aggr",
+                          "cnoc_sf_axi";
+
+            dma-coherent;
+
+            interrupts = <GIC_ESPI 205 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 206 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 207 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 208 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 209 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 210 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 211 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 212 IRQ_TYPE_LEVEL_HIGH>,
+                         <GIC_ESPI 204 IRQ_TYPE_LEVEL_HIGH>;
+            interrupt-names = "msi0", "msi1", "msi2", "msi3",
+                              "msi4", "msi5", "msi6", "msi7", "global";
+            #interrupt-cells = <1>;
+            interrupt-map-mask = <0 0 0 0x7>;
+            interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                            <0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                            <0 0 0 3 &intc 0 0 GIC_ESPI 215 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                            <0 0 0 4 &intc 0 0 GIC_ESPI 216 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+            interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
+                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+                            <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                             &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
+            interconnect-names = "pcie-mem", "cpu-pcie";
+
+            iommu-map = <0x0 &apps_smmu 0x1000 0x1>,
+                        <0x100 &apps_smmu 0x1001 0x1>;
+
+            pinctrl-0 = <&pcie0_default_state>;
+            pinctrl-names = "default";
+
+            power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
+
+            resets = <&gcc GCC_PCIE_0_BCR>,
+                     <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
+            reset-names = "pci", "link_down";
+
+            msi-map = <0x0 &gic_its 0x1000 0x1>,
+                      <0x100 &gic_its 0x1001 0x1>;
+            msi-map-mask = <0xff00>;
+
+            pcie@0 {
+                device_type = "pci";
+                reg = <0x0 0x0 0x0 0x0 0x0>;
+                bus-range = <0x01 0xff>;
+
+                #address-cells = <3>;
+                #size-cells = <2>;
+                ranges;
+
+                phys = <&pcie0_phy>;
+                wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
+                reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
+            };
+        };
+    };

-- 
2.34.1

Re: [PATCH 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The compatible string and filename violate the established Qualcomm PCIe naming pattern.
--

commit 332996956780b2d8736ee1fcd6b38c1627f71689
Author: Matthew Leung <matthew.leung@oss.qualcomm.com>

dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

Add a dedicated schema for the PCIe controllers found on the Hawi
platform.

> diff --git a/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
> new file mode 100644
> index 0000000000000..154bc88e59694
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml

This isn't a bug, but is there a reason this file isn't named
qcom,pcie-hawi.yaml? The rest of the Qualcomm PCIe Root Complex bindings
strictly follow the qcom,pcie-<soc> naming pattern, such as
qcom,pcie-sc7280.yaml and qcom,pcie-sm8550.yaml.

[ ... ]

> +properties:
> +  compatible:
> +    const: qcom,hawi-pcie

Should this compatible string also be changed to qcom,pcie-hawi to maintain
consistency with the other Qualcomm Root Complex definitions across the
subsystem?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260508-hawi-pcie-v1-0-0c910906f7e5@oss.qualcomm.com?part=1

Re: [PATCH 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[Rob Herring]

On Fri, May 08, 2026 at 01:21:34AM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Low] The compatible string and filename violate the established Qualcomm PCIe naming pattern.
> --
> 
> commit 332996956780b2d8736ee1fcd6b38c1627f71689
> Author: Matthew Leung <matthew.leung@oss.qualcomm.com>
> 
> dt-bindings: PCI: qcom: Document the Hawi PCIe Controller
> 
> Add a dedicated schema for the PCIe controllers found on the Hawi
> platform.
> 
> > diff --git a/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
> > new file mode 100644
> > index 0000000000000..154bc88e59694
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
> 
> This isn't a bug, but is there a reason this file isn't named
> qcom,pcie-hawi.yaml? The rest of the Qualcomm PCIe Root Complex bindings
> strictly follow the qcom,pcie-<soc> naming pattern, such as
> qcom,pcie-sc7280.yaml and qcom,pcie-sm8550.yaml.

Sashiko is wrong here.

> 
> [ ... ]
> 
> > +properties:
> > +  compatible:
> > +    const: qcom,hawi-pcie
> 
> Should this compatible string also be changed to qcom,pcie-hawi to maintain
> consistency with the other Qualcomm Root Complex definitions across the
> subsystem?
> 
> -- 
> Sashiko AI review · https://sashiko.dev/#/patchset/20260508-hawi-pcie-v1-0-0c910906f7e5@oss.qualcomm.com?part=1

Re: [PATCH 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[Rob Herring]

On Fri, May 08, 2026 at 01:02:14AM +0000, Matthew Leung wrote:
> Add a dedicated schema for the PCIe controllers found on the Hawi
> platform.
> 
> Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
> ---
>  .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 188 +++++++++++++++++++++
>  1 file changed, 188 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
> new file mode 100644
> index 000000000000..154bc88e5969
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
> @@ -0,0 +1,188 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/qcom,hawi-pcie.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Hawi PCI Express Root Complex
> +
> +maintainers:
> +  - Bjorn Andersson <andersson@kernel.org>
> +  - Manivannan Sadhasivam <mani@kernel.org>
> +
> +description:
> +  Qualcomm Hawi SoC (and compatible) PCIe root complex controller is based on
> +  the Synopsys DesignWare PCIe IP.
> +
> +properties:
> +  compatible:
> +    const: qcom,hawi-pcie
> +
> +  reg:
> +    minItems: 5
> +    maxItems: 6
> +
> +  reg-names:
> +    minItems: 5
> +    items:
> +      - const: parf # Qualcomm specific registers
> +      - const: dbi # DesignWare PCIe registers
> +      - const: elbi # External local bus interface registers
> +      - const: atu # ATU address space
> +      - const: config # PCIe configuration space
> +      - const: mhi # MHI registers
> +
> +  clocks:

minItems: 6

> +    maxItems: 7
> +
> +  clock-names:
> +    minItems: 6
> +    items:
> +      - const: aux # Auxiliary clock
> +      - const: cfg # Configuration clock
> +      - const: bus_master # Master AXI clock
> +      - const: bus_slave # Slave AXI clock
> +      - const: slave_q2a # Slave Q2A clock
> +      - const: noc_aggr # Aggre NoC PCIe AXI clock
> +      - const: cnoc_sf_axi # Config NoC PCIe0 AXI clock

Move all these description comments to 'description' entries under 
'clocks'. Same comment for 'reg-names'.

> +
> +  interrupts:
> +    minItems: 8
> +    maxItems: 9
> +
> +  interrupt-names:
> +    minItems: 8
> +    items:
> +      - const: msi0
> +      - const: msi1
> +      - const: msi2
> +      - const: msi3
> +      - const: msi4
> +      - const: msi5
> +      - const: msi6
> +      - const: msi7
> +      - const: global
> +
> +  resets:
> +    minItems: 1
> +    maxItems: 2
> +
> +  reset-names:
> +    minItems: 1
> +    items:
> +      - const: pci # PCIe core reset
> +      - const: link_down # PCIe link down reset

Same comment here.

> +
> +required:
> +  - power-domains
> +  - resets
> +  - reset-names
> +
> +allOf:
> +  - $ref: qcom,pcie-common.yaml#
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/qcom,hawi-gcc.h>
> +    #include <dt-bindings/gpio/gpio.h>
> +    #include <dt-bindings/interconnect/qcom,icc.h>
> +    #include <dt-bindings/interconnect/qcom,hawi-rpmh.h>
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    soc {
> +        #address-cells = <2>;
> +        #size-cells = <2>;
> +
> +        pcie@1c00000 {
> +            compatible = "qcom,hawi-pcie";
> +            reg = <0 0x01c00000 0 0x3000>,
> +                  <0 0x40000000 0 0xf1d>,
> +                  <0 0x40000f20 0 0xa8>,
> +                  <0 0x40001000 0 0x1000>,
> +                  <0 0x40100000 0 0x100000>;
> +            reg-names = "parf", "dbi", "elbi", "atu", "config";
> +            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
> +                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;
> +
> +            bus-range = <0x00 0xff>;
> +            device_type = "pci";
> +            linux,pci-domain = <0>;
> +            num-lanes = <2>;
> +
> +            #address-cells = <3>;
> +            #size-cells = <2>;
> +
> +            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
> +                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
> +                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
> +                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
> +                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
> +                     <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
> +                     <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
> +            clock-names = "aux",
> +                          "cfg",
> +                          "bus_master",
> +                          "bus_slave",
> +                          "slave_q2a",
> +                          "noc_aggr",
> +                          "cnoc_sf_axi";
> +
> +            dma-coherent;
> +
> +            interrupts = <GIC_ESPI 205 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_ESPI 206 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_ESPI 207 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_ESPI 208 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_ESPI 209 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_ESPI 210 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_ESPI 211 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_ESPI 212 IRQ_TYPE_LEVEL_HIGH>,
> +                         <GIC_ESPI 204 IRQ_TYPE_LEVEL_HIGH>;
> +            interrupt-names = "msi0", "msi1", "msi2", "msi3",
> +                              "msi4", "msi5", "msi6", "msi7", "global";
> +            #interrupt-cells = <1>;
> +            interrupt-map-mask = <0 0 0 0x7>;
> +            interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
> +                            <0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
> +                            <0 0 0 3 &intc 0 0 GIC_ESPI 215 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
> +                            <0 0 0 4 &intc 0 0 GIC_ESPI 216 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
> +
> +            interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
> +                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
> +                            <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> +                             &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
> +            interconnect-names = "pcie-mem", "cpu-pcie";
> +
> +            iommu-map = <0x0 &apps_smmu 0x1000 0x1>,
> +                        <0x100 &apps_smmu 0x1001 0x1>;
> +
> +            pinctrl-0 = <&pcie0_default_state>;
> +            pinctrl-names = "default";
> +
> +            power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
> +
> +            resets = <&gcc GCC_PCIE_0_BCR>,
> +                     <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
> +            reset-names = "pci", "link_down";
> +
> +            msi-map = <0x0 &gic_its 0x1000 0x1>,
> +                      <0x100 &gic_its 0x1001 0x1>;
> +            msi-map-mask = <0xff00>;
> +
> +            pcie@0 {
> +                device_type = "pci";
> +                reg = <0x0 0x0 0x0 0x0 0x0>;
> +                bus-range = <0x01 0xff>;
> +
> +                #address-cells = <3>;
> +                #size-cells = <2>;
> +                ranges;
> +
> +                phys = <&pcie0_phy>;
> +                wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
> +                reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
> +            };
> +        };
> +    };
> 
> -- 
> 2.34.1
> 

Re: [PATCH 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller

[Matthew Leung]

On 5/13/2026 3:56 PM, Rob Herring wrote:
> On Fri, May 08, 2026 at 01:02:14AM +0000, Matthew Leung wrote:
>> Add a dedicated schema for the PCIe controllers found on the Hawi
>> platform.
>>
>> Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
>> ---
>>  .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 188 +++++++++++++++++++++
>>  1 file changed, 188 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
>> new file mode 100644
>> index 000000000000..154bc88e5969
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml
>> @@ -0,0 +1,188 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/qcom,hawi-pcie.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm Hawi PCI Express Root Complex
>> +
>> +maintainers:
>> +  - Bjorn Andersson <andersson@kernel.org>
>> +  - Manivannan Sadhasivam <mani@kernel.org>
>> +
>> +description:
>> +  Qualcomm Hawi SoC (and compatible) PCIe root complex controller is based on
>> +  the Synopsys DesignWare PCIe IP.
>> +
>> +properties:
>> +  compatible:
>> +    const: qcom,hawi-pcie
>> +
>> +  reg:
>> +    minItems: 5
>> +    maxItems: 6
>> +
>> +  reg-names:
>> +    minItems: 5
>> +    items:
>> +      - const: parf # Qualcomm specific registers
>> +      - const: dbi # DesignWare PCIe registers
>> +      - const: elbi # External local bus interface registers
>> +      - const: atu # ATU address space
>> +      - const: config # PCIe configuration space
>> +      - const: mhi # MHI registers
>> +
>> +  clocks:
> 
> minItems: 6
> 

Will update.

>> +    maxItems: 7
>> +
>> +  clock-names:
>> +    minItems: 6
>> +    items:
>> +      - const: aux # Auxiliary clock
>> +      - const: cfg # Configuration clock
>> +      - const: bus_master # Master AXI clock
>> +      - const: bus_slave # Slave AXI clock
>> +      - const: slave_q2a # Slave Q2A clock
>> +      - const: noc_aggr # Aggre NoC PCIe AXI clock
>> +      - const: cnoc_sf_axi # Config NoC PCIe0 AXI clock
> 
> Move all these description comments to 'description' entries under 
> 'clocks'. Same comment for 'reg-names'.
> 

Thank you for the feedback. I will migrate the all of the description
comments into 'description' entries.

>> +
>> +  interrupts:
>> +    minItems: 8
>> +    maxItems: 9
>> +
>> +  interrupt-names:
>> +    minItems: 8
>> +    items:
>> +      - const: msi0
>> +      - const: msi1
>> +      - const: msi2
>> +      - const: msi3
>> +      - const: msi4
>> +      - const: msi5
>> +      - const: msi6
>> +      - const: msi7
>> +      - const: global
>> +
>> +  resets:
>> +    minItems: 1
>> +    maxItems: 2
>> +
>> +  reset-names:
>> +    minItems: 1
>> +    items:
>> +      - const: pci # PCIe core reset
>> +      - const: link_down # PCIe link down reset
> 
> Same comment here.
> 
>> +
>> +required:
>> +  - power-domains
>> +  - resets
>> +  - reset-names
>> +
>> +allOf:
>> +  - $ref: qcom,pcie-common.yaml#
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/clock/qcom,hawi-gcc.h>
>> +    #include <dt-bindings/gpio/gpio.h>
>> +    #include <dt-bindings/interconnect/qcom,icc.h>
>> +    #include <dt-bindings/interconnect/qcom,hawi-rpmh.h>
>> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +    soc {
>> +        #address-cells = <2>;
>> +        #size-cells = <2>;
>> +
>> +        pcie@1c00000 {
>> +            compatible = "qcom,hawi-pcie";
>> +            reg = <0 0x01c00000 0 0x3000>,
>> +                  <0 0x40000000 0 0xf1d>,
>> +                  <0 0x40000f20 0 0xa8>,
>> +                  <0 0x40001000 0 0x1000>,
>> +                  <0 0x40100000 0 0x100000>;
>> +            reg-names = "parf", "dbi", "elbi", "atu", "config";
>> +            ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
>> +                     <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;
>> +
>> +            bus-range = <0x00 0xff>;
>> +            device_type = "pci";
>> +            linux,pci-domain = <0>;
>> +            num-lanes = <2>;
>> +
>> +            #address-cells = <3>;
>> +            #size-cells = <2>;
>> +
>> +            clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
>> +                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
>> +                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
>> +                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
>> +                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
>> +                     <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
>> +                     <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;
>> +            clock-names = "aux",
>> +                          "cfg",
>> +                          "bus_master",
>> +                          "bus_slave",
>> +                          "slave_q2a",
>> +                          "noc_aggr",
>> +                          "cnoc_sf_axi";
>> +
>> +            dma-coherent;
>> +
>> +            interrupts = <GIC_ESPI 205 IRQ_TYPE_LEVEL_HIGH>,
>> +                         <GIC_ESPI 206 IRQ_TYPE_LEVEL_HIGH>,
>> +                         <GIC_ESPI 207 IRQ_TYPE_LEVEL_HIGH>,
>> +                         <GIC_ESPI 208 IRQ_TYPE_LEVEL_HIGH>,
>> +                         <GIC_ESPI 209 IRQ_TYPE_LEVEL_HIGH>,
>> +                         <GIC_ESPI 210 IRQ_TYPE_LEVEL_HIGH>,
>> +                         <GIC_ESPI 211 IRQ_TYPE_LEVEL_HIGH>,
>> +                         <GIC_ESPI 212 IRQ_TYPE_LEVEL_HIGH>,
>> +                         <GIC_ESPI 204 IRQ_TYPE_LEVEL_HIGH>;
>> +            interrupt-names = "msi0", "msi1", "msi2", "msi3",
>> +                              "msi4", "msi5", "msi6", "msi7", "global";
>> +            #interrupt-cells = <1>;
>> +            interrupt-map-mask = <0 0 0 0x7>;
>> +            interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
>> +                            <0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
>> +                            <0 0 0 3 &intc 0 0 GIC_ESPI 215 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
>> +                            <0 0 0 4 &intc 0 0 GIC_ESPI 216 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
>> +
>> +            interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS
>> +                             &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
>> +                            <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
>> +                             &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
>> +            interconnect-names = "pcie-mem", "cpu-pcie";
>> +
>> +            iommu-map = <0x0 &apps_smmu 0x1000 0x1>,
>> +                        <0x100 &apps_smmu 0x1001 0x1>;
>> +
>> +            pinctrl-0 = <&pcie0_default_state>;
>> +            pinctrl-names = "default";
>> +
>> +            power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;
>> +
>> +            resets = <&gcc GCC_PCIE_0_BCR>,
>> +                     <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
>> +            reset-names = "pci", "link_down";
>> +
>> +            msi-map = <0x0 &gic_its 0x1000 0x1>,
>> +                      <0x100 &gic_its 0x1001 0x1>;
>> +            msi-map-mask = <0xff00>;
>> +
>> +            pcie@0 {
>> +                device_type = "pci";
>> +                reg = <0x0 0x0 0x0 0x0 0x0>;
>> +                bus-range = <0x01 0xff>;
>> +
>> +                #address-cells = <3>;
>> +                #size-cells = <2>;
>> +                ranges;
>> +
>> +                phys = <&pcie0_phy>;
>> +                wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;
>> +                reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;
>> +            };
>> +        };
>> +    };
>>
>> -- 
>> 2.34.1
>>

[PATCH 2/2] PCI: qcom: Add support for Hawi

[Matthew Leung]

Add support for the Hawi platform which has two PCIe controllers: one
capable of Gen3 x2 operation and one capable of Gen4 x1 operation.

Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
---
 drivers/pci/controller/dwc/pcie-qcom.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index af6bf5cce65b..80a238aa26b6 100644
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -2121,6 +2121,7 @@ static int qcom_pcie_resume_noirq(struct device *dev)
 }
 
 static const struct of_device_id qcom_pcie_match[] = {
+	{ .compatible = "qcom,hawi-pcie", .data = &cfg_1_9_0 },
 	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
 	{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
 	{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },

-- 
2.34.1

Re: [PATCH 2/2] PCI: qcom: Add support for Hawi

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The introduced compatible string `qcom,hawi-pcie` deviates from the established `qcom,pcie-<soc>` naming convention.
--

commit 190903f616d8f4e9c8306f764cc2fdb2f6027cd6
Author: Matthew Leung <matthew.leung@oss.qualcomm.com>

PCI: qcom: Add support for Hawi

This commit adds support for the Hawi platform. It introduces a new device
tree match entry for the dual PCIe controllers present on the system.

> diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
> index af6bf5cce65be..80a238aa26b68 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom.c
> @@ -2121,6 +2121,7 @@ static int qcom_pcie_resume_noirq(struct device *dev)
>  }
>  
>  static const struct of_device_id qcom_pcie_match[] = {
> +	{ .compatible = "qcom,hawi-pcie", .data = &cfg_1_9_0 },

This isn't a bug, but should this compatible string follow the established
qcom,pcie- prefix format used by the other entries?

If renamed to qcom,pcie-hawi, would it also make sense to move this entry
further down in the array to maintain alphabetical sorting?

>  	{ .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
>  	{ .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
>  	{ .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260508-hawi-pcie-v1-0-0c910906f7e5@oss.qualcomm.com?part=2

Re: [PATCH 0/2] PCI: qcom: Add PCIe support for upcoming Hawi SoC

[Bjorn Helgaas]

On Fri, May 08, 2026 at 01:02:13AM +0000, Matthew Leung wrote:
> This series adds PCIe support for the Qualcomm Hawi SoC. The Hawi
> platform features two PCIe controllers: one capable of Gen3 x2 operation
> and one capable of Gen4 x1 operation. The first patch adds the device
> tree bindings documentation for the Hawi PCIe controller, and the second
> patch adds driver support by enabling the Hawi compatible string in the
> existing qcom PCIe driver.
> 
> This series depends on the following prerequisite series:
> - [PATCH v3 0/7] clk: qcom: Add initial clock controllers for the
>   upcoming Hawi SoC (Change-ID: 20260316-clk-hawi-1ad4cad36d6a:v3)
> - [PATCH v4 0/2] interconnect: qcom: Add support for upcoming Hawi SoC
>   (Change-ID: 20260311-icc-hawi-d6dc165f8935:v4)
> 
> These dependencies add necessary headers for running dt_binding_check
> against the binding.

These apply cleanly to v7.1-rc1.  I suppose the dt_binding_check thing
is the only real dependency?  Is there anything we need to do to
enforce the dependency when these get merged upstream during the merge
window?

> Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
> ---
> Matthew Leung (2):
>       dt-bindings: PCI: qcom: Document the Hawi PCIe Controller
>       PCI: qcom: Add support for Hawi
> 
>  .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 188 +++++++++++++++++++++
>  drivers/pci/controller/dwc/pcie-qcom.c             |   1 +
>  2 files changed, 189 insertions(+)
> ---
> base-commit: 4cd074ae20bbcc293bbbce9163abe99d68ae6ae0
> change-id: 20260506-hawi-pcie-f61435ca420c
> prerequisite-change-id: 20260316-clk-hawi-1ad4cad36d6a:v3
> prerequisite-patch-id: c4fbb0620d748d7f1ee675ade5167775bd31c8ac
> prerequisite-patch-id: ae5e212518cc333a1a93564cabfc6abd128df664
> prerequisite-patch-id: 3c3816e0d595589fc02383f10e48c83a61fdc9d1
> prerequisite-patch-id: cbc13fb819d1c1ee77957393f0958f05db8db864
> prerequisite-patch-id: 17e2c0cfbbea826fefa1c67d0f5dc2094ab73d76
> prerequisite-patch-id: 150dc74750377f4558deab6b179632872bcbb71c
> prerequisite-patch-id: 38fe0da5b18610aeb32c7154f9e50187ccaec6a4
> prerequisite-change-id: 20260311-icc-hawi-d6dc165f8935:v4
> prerequisite-patch-id: a1ff655f0b21d6259b158ad9f99a95bde31257e6
> prerequisite-patch-id: db21b6b20451be8475129faece7ef4191d41273c

I don't know where any of these change-ids or patch-ids come from.

Re: [PATCH 0/2] PCI: qcom: Add PCIe support for upcoming Hawi SoC

[Matthew Leung]

On Thu, May 14, 2026 at 12:21:51PM -0500, Bjorn Helgaas wrote:
> On Fri, May 08, 2026 at 01:02:13AM +0000, Matthew Leung wrote:
> > This series adds PCIe support for the Qualcomm Hawi SoC. The Hawi
> > platform features two PCIe controllers: one capable of Gen3 x2 operation
> > and one capable of Gen4 x1 operation. The first patch adds the device
> > tree bindings documentation for the Hawi PCIe controller, and the second
> > patch adds driver support by enabling the Hawi compatible string in the
> > existing qcom PCIe driver.
> > 
> > This series depends on the following prerequisite series:
> > - [PATCH v3 0/7] clk: qcom: Add initial clock controllers for the
> >   upcoming Hawi SoC (Change-ID: 20260316-clk-hawi-1ad4cad36d6a:v3)
> > - [PATCH v4 0/2] interconnect: qcom: Add support for upcoming Hawi SoC
> >   (Change-ID: 20260311-icc-hawi-d6dc165f8935:v4)
> > 
> > These dependencies add necessary headers for running dt_binding_check
> > against the binding.
> 
> These apply cleanly to v7.1-rc1.  I suppose the dt_binding_check thing
> is the only real dependency?  Is there anything we need to do to
> enforce the dependency when these get merged upstream during the merge
> window?
> 

Yes, the dependencies are only needed for running dt_binding_check as
the example dts snippet would produce an error on the missing headers.
The patches should apply and build cleanly otherwise.

I thought this check could be a problem for merging so added the
dependencies for completeness. If the binding check isn't a concern, I
can drop the dependencies.

> > Signed-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>
> > ---
> > Matthew Leung (2):
> >       dt-bindings: PCI: qcom: Document the Hawi PCIe Controller
> >       PCI: qcom: Add support for Hawi
> > 
> >  .../devicetree/bindings/pci/qcom,hawi-pcie.yaml    | 188 +++++++++++++++++++++
> >  drivers/pci/controller/dwc/pcie-qcom.c             |   1 +
> >  2 files changed, 189 insertions(+)
> > ---
> > base-commit: 4cd074ae20bbcc293bbbce9163abe99d68ae6ae0
> > change-id: 20260506-hawi-pcie-f61435ca420c
> > prerequisite-change-id: 20260316-clk-hawi-1ad4cad36d6a:v3
> > prerequisite-patch-id: c4fbb0620d748d7f1ee675ade5167775bd31c8ac
> > prerequisite-patch-id: ae5e212518cc333a1a93564cabfc6abd128df664
> > prerequisite-patch-id: 3c3816e0d595589fc02383f10e48c83a61fdc9d1
> > prerequisite-patch-id: cbc13fb819d1c1ee77957393f0958f05db8db864
> > prerequisite-patch-id: 17e2c0cfbbea826fefa1c67d0f5dc2094ab73d76
> > prerequisite-patch-id: 150dc74750377f4558deab6b179632872bcbb71c
> > prerequisite-patch-id: 38fe0da5b18610aeb32c7154f9e50187ccaec6a4
> > prerequisite-change-id: 20260311-icc-hawi-d6dc165f8935:v4
> > prerequisite-patch-id: a1ff655f0b21d6259b158ad9f99a95bde31257e6
> > prerequisite-patch-id: db21b6b20451be8475129faece7ef4191d41273c
> 
> I don't know where any of these change-ids or patch-ids come from.

These were generated by b4 after adding the change-id metadata for the
dependencies.

They should refer to the change-ids of the respective patch series:
- https://lore.kernel.org/all/20260506-clk-hawi-v3-0-530b538679f1@oss.qualcomm.com/
- https://lore.kernel.org/all/20260506-icc-hawi-v4-0-35447fdc482b@oss.qualcomm.com/