* [PATCH V2 1/5] PCI: Use cached Device Capabilities 2 Register
2021-05-11 15:08 [PATCH V2 0/5] PCI: Enable 10-Bit tag support for PCIe devices Dongdong Liu
@ 2021-05-11 15:09 ` Dongdong Liu
2021-05-11 15:26 ` Christoph Hellwig
2021-05-11 15:09 ` [PATCH V2 2/5] PCI: Add 10-Bit Tag register definitions Dongdong Liu
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Dongdong Liu @ 2021-05-11 15:09 UTC (permalink / raw)
To: helgaas, hch, linux-pci
It will make sense to store the devcap2 value in the pci_dev structure
instead of reading Device Capabilities 2 Register multiple times.
So we add pci_init_devcap2() to get the value of devcap2, then use
cached devcap2 in the needed place.
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 4 +---
drivers/pci/pci.c | 8 +++-----
drivers/pci/probe.c | 18 ++++++++++++------
include/linux/pci.h | 1 +
4 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 6264bc6..704d7c0 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -6303,7 +6303,6 @@ static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
struct pci_dev *pbridge;
struct port_info *pi;
char name[IFNAMSIZ];
- u32 devcap2;
u16 flags;
/* If we want to instantiate Virtual Functions, then our
@@ -6313,10 +6312,9 @@ static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
*/
pbridge = pdev->bus->self;
pcie_capability_read_word(pbridge, PCI_EXP_FLAGS, &flags);
- pcie_capability_read_dword(pbridge, PCI_EXP_DEVCAP2, &devcap2);
if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
- !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
+ !(pbridge->devcap2 & PCI_EXP_DEVCAP2_ARI)) {
/* Our parent bridge does not support ARI so issue a
* warning and skip instantiating the VFs. They
* won't be reachable.
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index b717680..ed219d7 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3690,7 +3690,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
{
struct pci_bus *bus = dev->bus;
struct pci_dev *bridge;
- u32 cap, ctl2;
+ u32 ctl2;
if (!pci_is_pcie(dev))
return -EINVAL;
@@ -3714,19 +3714,17 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
while (bus->parent) {
bridge = bus->self;
- pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
-
switch (pci_pcie_type(bridge)) {
/* Ensure switch ports support AtomicOp routing */
case PCI_EXP_TYPE_UPSTREAM:
case PCI_EXP_TYPE_DOWNSTREAM:
- if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
+ if (!(bridge->devcap2 & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
return -EINVAL;
break;
/* Ensure root port supports all the sizes we care about */
case PCI_EXP_TYPE_ROOT_PORT:
- if ((cap & cap_mask) != cap_mask)
+ if ((bridge->devcap2 & cap_mask) != cap_mask)
return -EINVAL;
break;
}
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 3a62d09..e66bc14 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2098,7 +2098,7 @@ static void pci_configure_ltr(struct pci_dev *dev)
#ifdef CONFIG_PCIEASPM
struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
struct pci_dev *bridge;
- u32 cap, ctl;
+ u32 ctl;
if (!pci_is_pcie(dev))
return;
@@ -2106,8 +2106,7 @@ static void pci_configure_ltr(struct pci_dev *dev)
/* Read L1 PM substate capabilities */
dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
- pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
- if (!(cap & PCI_EXP_DEVCAP2_LTR))
+ if (!(dev->devcap2 & PCI_EXP_DEVCAP2_LTR))
return;
pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
@@ -2147,13 +2146,11 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev)
#ifdef CONFIG_PCI_PASID
struct pci_dev *bridge;
int pcie_type;
- u32 cap;
if (!pci_is_pcie(dev))
return;
- pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
- if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
+ if (!(dev->devcap2 & PCI_EXP_DEVCAP2_EE_PREFIX))
return;
pcie_type = pci_pcie_type(dev);
@@ -2381,6 +2378,14 @@ void pcie_report_downtraining(struct pci_dev *dev)
__pcie_print_link_status(dev, false);
}
+static void pci_init_devcap2(struct pci_dev *dev)
+{
+ if (!pci_is_pcie(dev))
+ return;
+
+ pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &dev->devcap2);
+}
+
static void pci_init_capabilities(struct pci_dev *dev)
{
pci_ea_init(dev); /* Enhanced Allocation */
@@ -2457,6 +2462,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
{
int ret;
+ pci_init_devcap2(dev);
pci_configure_device(dev);
device_initialize(&dev->dev);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index c20211e..3244b0b 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -340,6 +340,7 @@ struct pci_dev {
u8 rom_base_reg; /* Config register controlling ROM */
u8 pin; /* Interrupt pin this device uses */
u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
+ u32 devcap2; /* Cached Device Capabilities 2 Register */
unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
struct pci_driver *driver; /* Driver bound to this device */
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH V2 1/5] PCI: Use cached Device Capabilities 2 Register
2021-05-11 15:09 ` [PATCH V2 1/5] PCI: Use cached Device Capabilities 2 Register Dongdong Liu
@ 2021-05-11 15:26 ` Christoph Hellwig
2021-05-12 7:29 ` Dongdong Liu
0 siblings, 1 reply; 8+ messages in thread
From: Christoph Hellwig @ 2021-05-11 15:26 UTC (permalink / raw)
To: Dongdong Liu; +Cc: helgaas, hch, linux-pci
On Tue, May 11, 2021 at 11:09:00PM +0800, Dongdong Liu wrote:
> It will make sense to store the devcap2 value in the pci_dev structure
> instead of reading Device Capabilities 2 Register multiple times.
> So we add pci_init_devcap2() to get the value of devcap2, then use
> cached devcap2 in the needed place.
This looks sensible. Should the devcap field maybe grow a pcie_
prefix? What about caching PCI_EXP_DEVCAP as well while you're at it?
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH V2 1/5] PCI: Use cached Device Capabilities 2 Register
2021-05-11 15:26 ` Christoph Hellwig
@ 2021-05-12 7:29 ` Dongdong Liu
0 siblings, 0 replies; 8+ messages in thread
From: Dongdong Liu @ 2021-05-12 7:29 UTC (permalink / raw)
To: Christoph Hellwig; +Cc: helgaas, linux-pci
Hi Christoph
Many thanks for your review.
On 2021/5/11 23:26, Christoph Hellwig wrote:
> On Tue, May 11, 2021 at 11:09:00PM +0800, Dongdong Liu wrote:
>> It will make sense to store the devcap2 value in the pci_dev structure
>> instead of reading Device Capabilities 2 Register multiple times.
>> So we add pci_init_devcap2() to get the value of devcap2, then use
>> cached devcap2 in the needed place.
>
> This looks sensible. Should the devcap field maybe grow a pcie_
> prefix?
Yes, It will be good to use pcie_prefix.
> What about caching PCI_EXP_DEVCAP as well while you're at it?
Make sense, will do.
Thanks,
Dongdong
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH V2 2/5] PCI: Add 10-Bit Tag register definitions
2021-05-11 15:08 [PATCH V2 0/5] PCI: Enable 10-Bit tag support for PCIe devices Dongdong Liu
2021-05-11 15:09 ` [PATCH V2 1/5] PCI: Use cached Device Capabilities 2 Register Dongdong Liu
@ 2021-05-11 15:09 ` Dongdong Liu
2021-05-11 15:09 ` [PATCH V2 3/5] PCI: Enable 10-Bit tag support for PCIe Endpoint devices Dongdong Liu
2021-05-11 15:09 ` [PATCH V2 4/5] PCI/IOV: Enable 10-Bit tag support for PCIe VF devices Dongdong Liu
3 siblings, 0 replies; 8+ messages in thread
From: Dongdong Liu @ 2021-05-11 15:09 UTC (permalink / raw)
To: helgaas, hch, linux-pci
Add 10-Bit Tag register definitions for use in subsequen patches.
See the PCIe 5.0 spec section 7.5.3.15 and 9.3.3.2.
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
---
include/uapi/linux/pci_regs.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index e709ae8..cf1ddb8 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -648,6 +648,8 @@
#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion */
#define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion */
#define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */
+#define PCI_EXP_DEVCAP2_10BIT_TAG_COMP 0x00010000 /* 10-Bit Tag Completer Supported */
+#define PCI_EXP_DEVCAP2_10BIT_TAG_REQ 0x00020000 /* 10-Bit Tag Requester Supported */
#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
@@ -661,6 +663,7 @@
#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */
+#define PCI_EXP_DEVCTL2_10BIT_TAG_REQ_EN 0x1000 /* 10-Bit Tag Requester Enable */
#define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 /* Enable OBFF Message type A */
#define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 /* Enable OBFF Message type B */
#define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
@@ -931,6 +934,7 @@
/* Single Root I/O Virtualization */
#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
#define PCI_SRIOV_CAP_VFM 0x00000001 /* VF Migration Capable */
+#define PCI_SRIOV_CAP_VF_10BIT_TAG_REQ 0x00000004 /* VF 10-Bit Tag Requester Supported */
#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */
#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
#define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */
@@ -938,6 +942,7 @@
#define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */
#define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */
#define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
+#define PCI_SRIOV_CTRL_VF_10BIT_TAG_REQ_EN 0x0020 /* VF 10-Bit Tag Requester Enable */
#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
#define PCI_SRIOV_STATUS_VFM 0x0001 /* VF Migration Status */
#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH V2 3/5] PCI: Enable 10-Bit tag support for PCIe Endpoint devices
2021-05-11 15:08 [PATCH V2 0/5] PCI: Enable 10-Bit tag support for PCIe devices Dongdong Liu
2021-05-11 15:09 ` [PATCH V2 1/5] PCI: Use cached Device Capabilities 2 Register Dongdong Liu
2021-05-11 15:09 ` [PATCH V2 2/5] PCI: Add 10-Bit Tag register definitions Dongdong Liu
@ 2021-05-11 15:09 ` Dongdong Liu
2021-05-11 15:09 ` [PATCH V2 4/5] PCI/IOV: Enable 10-Bit tag support for PCIe VF devices Dongdong Liu
3 siblings, 0 replies; 8+ messages in thread
From: Dongdong Liu @ 2021-05-11 15:09 UTC (permalink / raw)
To: helgaas, hch, linux-pci
10-Bit Tag capability, introduced in PCIe-4.0 increases the total Tag
field size from 8 bits to 10 bits.
For platforms where the RC supports 10-Bit Tag Completer capability,
it is highly recommended for platform firmware or operating software
that configures PCIe hierarchies to Set the 10-Bit Tag Requester Enable
bit automatically in Endpoints with 10-Bit Tag Requester capability. This
enables the important class of 10-Bit Tag capable adapters that send
Memory Read Requests only to host memory.
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
---
drivers/pci/probe.c | 36 ++++++++++++++++++++++++++++++++++++
include/linux/pci.h | 2 ++
2 files changed, 38 insertions(+)
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index e66bc14..b48b41f 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2051,6 +2051,41 @@ int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
return 0;
}
+static void pci_configure_10bit_tags(struct pci_dev *dev)
+{
+ struct pci_dev *bridge;
+
+ if (!pci_is_pcie(dev))
+ return;
+
+ if (!(dev->devcap2 & PCI_EXP_DEVCAP2_10BIT_TAG_COMP))
+ return;
+
+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
+ dev->ext_10bit_tag = 1;
+ return;
+ }
+
+ bridge = pci_upstream_bridge(dev);
+ if (bridge && bridge->ext_10bit_tag)
+ dev->ext_10bit_tag = 1;
+
+ /*
+ * 10-Bit Tag Requester Enable in Device Control 2 Register is RsvdP
+ * for VF.
+ */
+ if (dev->is_virtfn)
+ return;
+
+ if (pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT &&
+ dev->ext_10bit_tag == 1 &&
+ (dev->devcap2 & PCI_EXP_DEVCAP2_10BIT_TAG_REQ)) {
+ pci_dbg(dev, "enabling 10-Bit Tag Requester\n");
+ pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
+ PCI_EXP_DEVCTL2_10BIT_TAG_REQ_EN);
+ }
+}
+
/**
* pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
* @dev: PCI device to query
@@ -2187,6 +2222,7 @@ static void pci_configure_device(struct pci_dev *dev)
{
pci_configure_mps(dev);
pci_configure_extended_tags(dev, NULL);
+ pci_configure_10bit_tags(dev);
pci_configure_relaxed_ordering(dev);
pci_configure_ltr(dev);
pci_configure_eetlp_prefix(dev);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 3244b0b..7c74d64 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -391,6 +391,8 @@ struct pci_dev {
#endif
unsigned int eetlp_prefix_path:1; /* End-to-End TLP Prefix */
+ unsigned int ext_10bit_tag:1; /* 10-Bit Tag Completer Supported
+ from root to here */
pci_channel_state_t error_state; /* Current connectivity state */
struct device dev; /* Generic device interface */
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH V2 4/5] PCI/IOV: Enable 10-Bit tag support for PCIe VF devices
2021-05-11 15:08 [PATCH V2 0/5] PCI: Enable 10-Bit tag support for PCIe devices Dongdong Liu
` (2 preceding siblings ...)
2021-05-11 15:09 ` [PATCH V2 3/5] PCI: Enable 10-Bit tag support for PCIe Endpoint devices Dongdong Liu
@ 2021-05-11 15:09 ` Dongdong Liu
3 siblings, 0 replies; 8+ messages in thread
From: Dongdong Liu @ 2021-05-11 15:09 UTC (permalink / raw)
To: helgaas, hch, linux-pci
Enable VF 10-Bit Tag Requester when it's upstream component support
10-bit Tag Completer.
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
---
drivers/pci/iov.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/pci/iov.c b/drivers/pci/iov.c
index afc06e6..3eb4348 100644
--- a/drivers/pci/iov.c
+++ b/drivers/pci/iov.c
@@ -627,6 +627,10 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
pci_iov_set_numvfs(dev, nr_virtfn);
iov->ctrl |= PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE;
+ if ((iov->cap & PCI_SRIOV_CAP_VF_10BIT_TAG_REQ) &&
+ dev->ext_10bit_tag)
+ iov->ctrl |= PCI_SRIOV_CTRL_VF_10BIT_TAG_REQ_EN;
+
pci_cfg_access_lock(dev);
pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
msleep(100);
@@ -643,6 +647,8 @@ static int sriov_enable(struct pci_dev *dev, int nr_virtfn)
err_pcibios:
iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
+ if (iov->ctrl & PCI_SRIOV_CTRL_VF_10BIT_TAG_REQ_EN)
+ iov->ctrl &= ~PCI_SRIOV_CTRL_VF_10BIT_TAG_REQ_EN;
pci_cfg_access_lock(dev);
pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
ssleep(1);
@@ -675,6 +681,8 @@ static void sriov_disable(struct pci_dev *dev)
sriov_del_vfs(dev);
iov->ctrl &= ~(PCI_SRIOV_CTRL_VFE | PCI_SRIOV_CTRL_MSE);
+ if (iov->ctrl & PCI_SRIOV_CTRL_VF_10BIT_TAG_REQ_EN)
+ iov->ctrl &= ~PCI_SRIOV_CTRL_VF_10BIT_TAG_REQ_EN;
pci_cfg_access_lock(dev);
pci_write_config_word(dev, iov->pos + PCI_SRIOV_CTRL, iov->ctrl);
ssleep(1);
--
2.7.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH V2 1/5] PCI: Use cached Device Capabilities 2 Register
2021-05-11 13:59 [PATCH V2 0/5] PCI: Enable 10-Bit tag support for PCIe devices Dongdong Liu
@ 2021-05-11 13:59 ` Dongdong Liu
0 siblings, 0 replies; 8+ messages in thread
From: Dongdong Liu @ 2021-05-11 13:59 UTC (permalink / raw)
To: helgaas, hch, linux-pci; +Cc: Dongdong Liu
It will make sense to store the devcap2 value in the pci_dev structure
instead of reading Device Capabilities 2 Register multiple times.
So we add pci_init_devcap2() to get the value of devcap2, then use
cached devcap2 in the needed place.
Signed-off-by: Dongdong Liu <liudongdong3@huawei.com>
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 4 +---
drivers/pci/pci.c | 8 +++-----
drivers/pci/probe.c | 18 ++++++++++++------
include/linux/pci.h | 1 +
4 files changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 6264bc6..704d7c0 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -6303,7 +6303,6 @@ static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
struct pci_dev *pbridge;
struct port_info *pi;
char name[IFNAMSIZ];
- u32 devcap2;
u16 flags;
/* If we want to instantiate Virtual Functions, then our
@@ -6313,10 +6312,9 @@ static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
*/
pbridge = pdev->bus->self;
pcie_capability_read_word(pbridge, PCI_EXP_FLAGS, &flags);
- pcie_capability_read_dword(pbridge, PCI_EXP_DEVCAP2, &devcap2);
if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
- !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
+ !(pbridge->devcap2 & PCI_EXP_DEVCAP2_ARI)) {
/* Our parent bridge does not support ARI so issue a
* warning and skip instantiating the VFs. They
* won't be reachable.
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index b717680..ed219d7 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3690,7 +3690,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
{
struct pci_bus *bus = dev->bus;
struct pci_dev *bridge;
- u32 cap, ctl2;
+ u32 ctl2;
if (!pci_is_pcie(dev))
return -EINVAL;
@@ -3714,19 +3714,17 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
while (bus->parent) {
bridge = bus->self;
- pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
-
switch (pci_pcie_type(bridge)) {
/* Ensure switch ports support AtomicOp routing */
case PCI_EXP_TYPE_UPSTREAM:
case PCI_EXP_TYPE_DOWNSTREAM:
- if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
+ if (!(bridge->devcap2 & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
return -EINVAL;
break;
/* Ensure root port supports all the sizes we care about */
case PCI_EXP_TYPE_ROOT_PORT:
- if ((cap & cap_mask) != cap_mask)
+ if ((bridge->devcap2 & cap_mask) != cap_mask)
return -EINVAL;
break;
}
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 3a62d09..e66bc14 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2098,7 +2098,7 @@ static void pci_configure_ltr(struct pci_dev *dev)
#ifdef CONFIG_PCIEASPM
struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
struct pci_dev *bridge;
- u32 cap, ctl;
+ u32 ctl;
if (!pci_is_pcie(dev))
return;
@@ -2106,8 +2106,7 @@ static void pci_configure_ltr(struct pci_dev *dev)
/* Read L1 PM substate capabilities */
dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
- pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
- if (!(cap & PCI_EXP_DEVCAP2_LTR))
+ if (!(dev->devcap2 & PCI_EXP_DEVCAP2_LTR))
return;
pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
@@ -2147,13 +2146,11 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev)
#ifdef CONFIG_PCI_PASID
struct pci_dev *bridge;
int pcie_type;
- u32 cap;
if (!pci_is_pcie(dev))
return;
- pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
- if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
+ if (!(dev->devcap2 & PCI_EXP_DEVCAP2_EE_PREFIX))
return;
pcie_type = pci_pcie_type(dev);
@@ -2381,6 +2378,14 @@ void pcie_report_downtraining(struct pci_dev *dev)
__pcie_print_link_status(dev, false);
}
+static void pci_init_devcap2(struct pci_dev *dev)
+{
+ if (!pci_is_pcie(dev))
+ return;
+
+ pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &dev->devcap2);
+}
+
static void pci_init_capabilities(struct pci_dev *dev)
{
pci_ea_init(dev); /* Enhanced Allocation */
@@ -2457,6 +2462,7 @@ void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
{
int ret;
+ pci_init_devcap2(dev);
pci_configure_device(dev);
device_initialize(&dev->dev);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index c20211e..3244b0b 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -340,6 +340,7 @@ struct pci_dev {
u8 rom_base_reg; /* Config register controlling ROM */
u8 pin; /* Interrupt pin this device uses */
u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
+ u32 devcap2; /* Cached Device Capabilities 2 Register */
unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
struct pci_driver *driver; /* Driver bound to this device */
--
2.7.4
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