Re: [RFC 2/6] drm/xe/vrsr: Detect vrsr capability

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Mon, Feb 24, 2025 at 10:18:45PM +0530, Anshuman Gupta wrote:
> Detect VRAM Self Refresh(vrsr) Capability.
> 
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_regs.h    |  3 +++
>  drivers/gpu/drm/xe/xe_device_types.h |  4 ++++
>  drivers/gpu/drm/xe/xe_pm.c           | 27 +++++++++++++++++++++++++++
>  3 files changed, 34 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 6cf282618836..21563e9d958b 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -57,6 +57,9 @@
>  #define MTL_MPE_FREQUENCY			XE_REG(0x13802c)
>  #define   MTL_RPE_MASK				REG_GENMASK(8, 0)
>  
> +#define VRAM_CAPABILITY                         XE_REG(0x138144)
> +#define   VRAM_SUPPORTED                        REG_BIT(0)

I'm missing a 'SR' mention here.

I know the register name is VRAM_CAPABILITY what looks horrible, but let's live with
it, but we could then use same or similar terminology from BSPec:

VRAM_SR_CAP

or VRAM_SR_CAP_SUPPORTED

or VRAM_SR_SUPPORTED at least?

with some mention to SR here:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> +
>  #define VF_CAP_REG				XE_REG(0x1901f8, XE_REG_OPTION_VF)
>  #define   VF_CAP				REG_BIT(0)
>  
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index 4656305dd45a..c2ab2c91c968 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -490,6 +490,9 @@ struct xe_device {
>  		/** @d3cold.allowed: Indicates if d3cold is a valid device state */
>  		bool allowed;
>  
> +		/** @d3cold.vrsr_capable: Indicates if d3cold VRAM Self Refresh is supported */
> +		bool vrsr_capable;
> +
>  		/**
>  		 * @d3cold.vram_threshold:
>  		 *
> @@ -500,6 +503,7 @@ struct xe_device {
>  		 * Default threshold value is 300mb.
>  		 */
>  		u32 vram_threshold;
> +
>  		/** @d3cold.lock: protect vram_threshold */
>  		struct mutex lock;
>  	} d3cold;
> diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
> index 12200be7b43d..dead236355d8 100644
> --- a/drivers/gpu/drm/xe/xe_pm.c
> +++ b/drivers/gpu/drm/xe/xe_pm.c
> @@ -17,12 +17,15 @@
>  #include "xe_bo_evict.h"
>  #include "xe_device.h"
>  #include "xe_device_sysfs.h"
> +#include "xe_force_wake.h"
>  #include "xe_ggtt.h"
>  #include "xe_gt.h"
>  #include "xe_guc.h"
>  #include "xe_irq.h"
> +#include "xe_mmio.h"
>  #include "xe_pcode.h"
>  #include "xe_pxp.h"
> +#include "regs/xe_regs.h"
>  #include "xe_trace.h"
>  #include "xe_wa.h"
>  
> @@ -236,6 +239,28 @@ static bool xe_pm_pci_d3cold_capable(struct xe_device *xe)
>  	return true;
>  }
>  
> +static bool xe_pm_vrsr_capable(struct xe_device *xe)
> +{
> +	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
> +	unsigned int fw_ref;
> +	struct xe_gt *gt;
> +	u32 val;
> +
> +	gt = xe_root_mmio_gt(xe);
> +
> +	if (!xe->info.probe_display)
> +		return false;
> +
> +	fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL);
> +	if (!fw_ref)
> +		return false;
> +
> +	val = xe_mmio_read32(mmio, VRAM_CAPABILITY);
> +	xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL);
> +
> +	return val & VRAM_SUPPORTED;
> +}
> +
>  static void xe_pm_runtime_init(struct xe_device *xe)
>  {
>  	struct device *dev = xe->drm.dev;
> @@ -303,6 +328,8 @@ int xe_pm_init(struct xe_device *xe)
>  		err = xe_pm_set_vram_threshold(xe, DEFAULT_VRAM_THRESHOLD);
>  		if (err)
>  			return err;
> +
> +		xe->d3cold.vrsr_capable = xe_pm_vrsr_capable(xe);
>  	}
>  
>  	xe_pm_runtime_init(xe);
> -- 
> 2.34.1
>