Re: [PATCH] PCI: tegra194: Reset BARs when running in PCIe endpoint mode

[Niklas Cassel <cassel@kernel.org>]

On Sat, Sep 20, 2025 at 09:04:01PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Sep 19, 2025 at 03:16:47PM +0200, Niklas Cassel wrote:
> > Tegra already defines all BARs expect for BAR0 as BAR_RESERVED.
> > This is sufficient for pci-epf-test to not allocate backing memory and to
> > not call set_bar() for those BARs.
> > 
> > However, the host side driver, pci_endpoint_test, simply does an ioremap
> > for all enabled BARs, and will run tests against all enabled BARs.
> > 
> > After running the BARs tests (which will write to all enabled BARs), the
> > inbound address translation is broken.
> > This is because the tegra controller exposes the ATU Port Logic Structure
> > in BAR4. So when BAR4 is written, the inbound address translation settings
> > get overwritten.
> > 
> 
> BAR4 or BAR0?

BAR4.
Just because a BAR is marked as BAR_RESERVED does not mean that the BAR is
disabled. Hence this patch.
I can make this clearer in V2.

I think a better solution would be for pci-epf-test to actually do something
like call a .disable_bar() for BARs that are marked as BAR_RESERVED.

But, implementing this callback is non-trivial, especially for non-DWC based
drivers where we dont have an equivalent to dw_pcie_ep_reset_bar().
Thus, I chose to keep with the existing convention of calling
dw_pcie_ep_reset_bar() in the .init callback, like it is done for all other
DWC-based EPC drivers.


Kind regards,
Niklas