[PATCH] PCI: tegra194: Reset BARs when running in PCIe endpoint mode

[PATCH] PCI: tegra194: Reset BARs when running in PCIe endpoint mode

[Niklas Cassel]

Tegra already defines all BARs expect for BAR0 as BAR_RESERVED.
This is sufficient for pci-epf-test to not allocate backing memory and to
not call set_bar() for those BARs.

However, the host side driver, pci_endpoint_test, simply does an ioremap
for all enabled BARs, and will run tests against all enabled BARs.

After running the BARs tests (which will write to all enabled BARs), the
inbound address translation is broken.
This is because the tegra controller exposes the ATU Port Logic Structure
in BAR4. So when BAR4 is written, the inbound address translation settings
get overwritten.

To avoid this, implement the dw_pcie_ep_ops .init() callback and start off
by disabling all BARs (pci-epf-test will later enable/configure BARs that
are not defined as BAR_RESERVED).

This matches the behavior of other PCIe endpoint drivers:
dra7xx, imx6, layerscape-ep, artpec6, dw-rockchip, qcom-ep, rcar-gen4, and
uniphier-ep.

With this, the PCI endpoint kselftest test case CONSECUTIVE_BAR_TEST
(which was specifically made to detect address translation issues) passes.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 4f26086f25daf..9488805ecf608 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1941,6 +1941,15 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
+static void tegra_pcie_ep_init(struct dw_pcie_ep *ep)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+	enum pci_barno bar;
+
+	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
+		dw_pcie_ep_reset_bar(pci, bar);
+};
+
 static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
 {
 	/* Tegra194 supports only INTA */
@@ -2017,6 +2026,7 @@ tegra_pcie_ep_get_features(struct dw_pcie_ep *ep)
 }
 
 static const struct dw_pcie_ep_ops pcie_ep_ops = {
+	.init = tegra_pcie_ep_init,
 	.raise_irq = tegra_pcie_ep_raise_irq,
 	.get_features = tegra_pcie_ep_get_features,
 };
-- 
2.51.0

Re: [PATCH] PCI: tegra194: Reset BARs when running in PCIe endpoint mode

[Manivannan Sadhasivam]

On Fri, Sep 19, 2025 at 03:16:47PM +0200, Niklas Cassel wrote:
> Tegra already defines all BARs expect for BAR0 as BAR_RESERVED.
> This is sufficient for pci-epf-test to not allocate backing memory and to
> not call set_bar() for those BARs.
> 
> However, the host side driver, pci_endpoint_test, simply does an ioremap
> for all enabled BARs, and will run tests against all enabled BARs.
> 
> After running the BARs tests (which will write to all enabled BARs), the
> inbound address translation is broken.
> This is because the tegra controller exposes the ATU Port Logic Structure
> in BAR4. So when BAR4 is written, the inbound address translation settings
> get overwritten.
> 

BAR4 or BAR0?

- Mani

> To avoid this, implement the dw_pcie_ep_ops .init() callback and start off
> by disabling all BARs (pci-epf-test will later enable/configure BARs that
> are not defined as BAR_RESERVED).
> 
> This matches the behavior of other PCIe endpoint drivers:
> dra7xx, imx6, layerscape-ep, artpec6, dw-rockchip, qcom-ep, rcar-gen4, and
> uniphier-ep.
> 
> With this, the PCI endpoint kselftest test case CONSECUTIVE_BAR_TEST
> (which was specifically made to detect address translation issues) passes.
> 
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
>  drivers/pci/controller/dwc/pcie-tegra194.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 4f26086f25daf..9488805ecf608 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1941,6 +1941,15 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)
>  	return IRQ_HANDLED;
>  }
>  
> +static void tegra_pcie_ep_init(struct dw_pcie_ep *ep)
> +{
> +	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> +	enum pci_barno bar;
> +
> +	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> +		dw_pcie_ep_reset_bar(pci, bar);
> +};
> +
>  static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
>  {
>  	/* Tegra194 supports only INTA */
> @@ -2017,6 +2026,7 @@ tegra_pcie_ep_get_features(struct dw_pcie_ep *ep)
>  }
>  
>  static const struct dw_pcie_ep_ops pcie_ep_ops = {
> +	.init = tegra_pcie_ep_init,
>  	.raise_irq = tegra_pcie_ep_raise_irq,
>  	.get_features = tegra_pcie_ep_get_features,
>  };
> -- 
> 2.51.0
> 

-- 
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Re: [PATCH] PCI: tegra194: Reset BARs when running in PCIe endpoint mode

[Niklas Cassel]

On Sat, Sep 20, 2025 at 09:04:01PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Sep 19, 2025 at 03:16:47PM +0200, Niklas Cassel wrote:
> > Tegra already defines all BARs expect for BAR0 as BAR_RESERVED.
> > This is sufficient for pci-epf-test to not allocate backing memory and to
> > not call set_bar() for those BARs.
> > 
> > However, the host side driver, pci_endpoint_test, simply does an ioremap
> > for all enabled BARs, and will run tests against all enabled BARs.
> > 
> > After running the BARs tests (which will write to all enabled BARs), the
> > inbound address translation is broken.
> > This is because the tegra controller exposes the ATU Port Logic Structure
> > in BAR4. So when BAR4 is written, the inbound address translation settings
> > get overwritten.
> > 
> 
> BAR4 or BAR0?

BAR4.
Just because a BAR is marked as BAR_RESERVED does not mean that the BAR is
disabled. Hence this patch.
I can make this clearer in V2.

I think a better solution would be for pci-epf-test to actually do something
like call a .disable_bar() for BARs that are marked as BAR_RESERVED.

But, implementing this callback is non-trivial, especially for non-DWC based
drivers where we dont have an equivalent to dw_pcie_ep_reset_bar().
Thus, I chose to keep with the existing convention of calling
dw_pcie_ep_reset_bar() in the .init callback, like it is done for all other
DWC-based EPC drivers.


Kind regards,
Niklas

Re: [PATCH] PCI: tegra194: Reset BARs when running in PCIe endpoint mode

[Manivannan Sadhasivam]

On Mon, Sep 22, 2025 at 03:06:57PM +0200, Niklas Cassel wrote:
> On Sat, Sep 20, 2025 at 09:04:01PM +0530, Manivannan Sadhasivam wrote:
> > On Fri, Sep 19, 2025 at 03:16:47PM +0200, Niklas Cassel wrote:
> > > Tegra already defines all BARs expect for BAR0 as BAR_RESERVED.
> > > This is sufficient for pci-epf-test to not allocate backing memory and to
> > > not call set_bar() for those BARs.
> > > 
> > > However, the host side driver, pci_endpoint_test, simply does an ioremap
> > > for all enabled BARs, and will run tests against all enabled BARs.
> > > 
> > > After running the BARs tests (which will write to all enabled BARs), the
> > > inbound address translation is broken.
> > > This is because the tegra controller exposes the ATU Port Logic Structure
> > > in BAR4. So when BAR4 is written, the inbound address translation settings
> > > get overwritten.
> > > 
> > 
> > BAR4 or BAR0?
> 
> BAR4.
> Just because a BAR is marked as BAR_RESERVED does not mean that the BAR is
> disabled. Hence this patch.
> I can make this clearer in V2.
> 

First paragraph says that BAR0 is marked as BAR_RESERVED, and here you were
saying BAR4, hence I asked the question without cross checking the driver. Now,
I checked the driver and I think you mistakenly said BAR0 instead of BAR4.

> I think a better solution would be for pci-epf-test to actually do something
> like call a .disable_bar() for BARs that are marked as BAR_RESERVED.
> 
> But, implementing this callback is non-trivial, especially for non-DWC based
> drivers where we dont have an equivalent to dw_pcie_ep_reset_bar().
> Thus, I chose to keep with the existing convention of calling
> dw_pcie_ep_reset_bar() in the .init callback, like it is done for all other
> DWC-based EPC drivers.
> 

That's fine. I was just pointing out the discrepancy.

- Mani

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Re: [PATCH] PCI: tegra194: Reset BARs when running in PCIe endpoint mode

[Manivannan Sadhasivam]

On Wed, Sep 24, 2025 at 09:27:48PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Sep 22, 2025 at 03:06:57PM +0200, Niklas Cassel wrote:
> > On Sat, Sep 20, 2025 at 09:04:01PM +0530, Manivannan Sadhasivam wrote:
> > > On Fri, Sep 19, 2025 at 03:16:47PM +0200, Niklas Cassel wrote:
> > > > Tegra already defines all BARs expect for BAR0 as BAR_RESERVED.
> > > > This is sufficient for pci-epf-test to not allocate backing memory and to
> > > > not call set_bar() for those BARs.
> > > > 
> > > > However, the host side driver, pci_endpoint_test, simply does an ioremap
> > > > for all enabled BARs, and will run tests against all enabled BARs.
> > > > 
> > > > After running the BARs tests (which will write to all enabled BARs), the
> > > > inbound address translation is broken.
> > > > This is because the tegra controller exposes the ATU Port Logic Structure
> > > > in BAR4. So when BAR4 is written, the inbound address translation settings
> > > > get overwritten.
> > > > 
> > > 
> > > BAR4 or BAR0?
> > 
> > BAR4.
> > Just because a BAR is marked as BAR_RESERVED does not mean that the BAR is
> > disabled. Hence this patch.
> > I can make this clearer in V2.
> > 
> 
> First paragraph says that BAR0 is marked as BAR_RESERVED, and here you were
> saying BAR4, hence I asked the question without cross checking the driver. Now,
> I checked the driver and I think you mistakenly said BAR0 instead of BAR4.
> 

Oops.. I misread it, actually. All fine.

- Mani

-- 
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