Re: [PATCH v2 1/2] PCI: dw-rockchip: Add L1sub support

[Shawn Lin <shawn.lin@rock-chips.com>]

在 2025/10/22 星期三 19:52, Hans Zhang 写道:
> 
> 
> On 10/22/2025 7:35 PM, Shawn Lin wrote:
>> EXTERNAL EMAIL
>>
>> The driver should set app_clk_req_n(clkreq ready) of PCIE_CLIENT_POWER 
>> reg
>> to support L1sub. Otherwise, unset app_clk_req_n and pull down CLKREQ#.
>>
>> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
>>
>> ---
>>
>> Changes in v2:
>> - drop of_pci_clkreq_presnt API
>> - drop dependency of Niklas's patch
>>
>>   drivers/pci/controller/dwc/pcie-dw-rockchip.c | 36 +++++++++++++++++ 
>> ++++++++++
>>   1 file changed, 36 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/ 
>> pci/controller/dwc/pcie-dw-rockchip.c
>> index 3e2752c..18cd626 100644
>> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
>> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
>> @@ -62,6 +62,12 @@
>>   /* Interrupt Mask Register Related to Miscellaneous Operation */
>>   #define PCIE_CLIENT_INTR_MASK_MISC     0x24
>>
>> +/* Power Management Control Register */
>> +#define PCIE_CLIENT_POWER              0x2c
>> +#define  PCIE_CLKREQ_READY             0x10001
>> +#define  PCIE_CLKREQ_NOT_READY         0x10000
>> +#define  PCIE_CLKREQ_PULL_DOWN         0x30001000
>> +
>>   /* Hot Reset Control Register */
>>   #define PCIE_CLIENT_HOT_RESET_CTRL     0x180
>>   #define  PCIE_LTSSM_APP_DLY2_EN                BIT(1)
>> @@ -85,6 +91,7 @@ struct rockchip_pcie {
>>          struct regulator *vpcie3v3;
>>          struct irq_domain *irq_domain;
>>          const struct rockchip_pcie_of_data *data;
>> +       bool supports_clkreq;
>>   };
>>
>>   struct rockchip_pcie_of_data {
>> @@ -200,6 +207,31 @@ static bool rockchip_pcie_link_up(struct dw_pcie 
>> *pci)
>>          return FIELD_GET(PCIE_LINKUP_MASK, val) == PCIE_LINKUP;
>>   }
>>
>> +static void rockchip_pcie_enable_l1sub(struct dw_pcie *pci)
>> +{
>> +       struct rockchip_pcie *rockchip = to_rockchip_pcie(pci);
>> +       u32 cap, l1subcap;
>> +
>> +       /* Enable L1 substates if CLKREQ# is properly connected */
>> +       if (rockchip->supports_clkreq) {
>> +               /* Ready to have reference clock removed */
>> +               rockchip_pcie_writel_apb(rockchip, PCIE_CLKREQ_READY, 
>> PCIE_CLIENT_POWER);
>> +               return;
>> +       }
>> +
>> +       /* Otherwise, pull down CLKREQ# and disable L1 substates */
>> +       rockchip_pcie_writel_apb(rockchip, PCIE_CLKREQ_PULL_DOWN | 
>> PCIE_CLKREQ_NOT_READY,
>> +                                PCIE_CLIENT_POWER);
>> +       cap = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS);
>> +       if (cap) {
>> +               l1subcap = dw_pcie_readl_dbi(pci, cap + PCI_L1SS_CAP);
>> +               l1subcap &= ~(PCI_L1SS_CAP_L1_PM_SS | 
>> PCI_L1SS_CAP_ASPM_L1_1 |
>> +                             PCI_L1SS_CAP_ASPM_L1_2 | 
>> PCI_L1SS_CAP_PCIPM_L1_1 |
>> +                             PCI_L1SS_CAP_PCIPM_L1_2);
>> +               dw_pcie_writel_dbi(pci, cap + PCI_L1SS_CAP, l1subcap);
>> +       }
>> +}
>> +
>>   static void rockchip_pcie_enable_l0s(struct dw_pcie *pci)
>>   {
>>          u32 cap, lnkcap;
>> @@ -264,6 +296,7 @@ static int rockchip_pcie_host_init(struct 
>> dw_pcie_rp *pp)
>>          irq_set_chained_handler_and_data(irq, 
>> rockchip_pcie_intx_handler,
>>                                           rockchip);
>>
>> +       rockchip_pcie_enable_l1sub(pci);
>>          rockchip_pcie_enable_l0s(pci);
>>
>>          return 0;
>> @@ -301,6 +334,7 @@ static void rockchip_pcie_ep_init(struct 
>> dw_pcie_ep *ep)
>>          struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>>          enum pci_barno bar;
>>
>> +       rockchip_pcie_enable_l1sub(pci);
>>          rockchip_pcie_enable_l0s(pci);
>>          rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep);
>>
>> @@ -412,6 +446,8 @@ static int rockchip_pcie_resource_get(struct 
>> platform_device *pdev,
>>                  return dev_err_probe(&pdev->dev, PTR_ERR(rockchip->rst),
>>                                       "failed to get reset lines\n");
>>
>> +       rockchip->supports_clkreq = of_property_read_bool(pdev- 
>> >dev.of_node, "supports-clkreq");
> 
> Hi Shawn,
> 
> This line exceeds 80 characters. Can it be like this?
> 

Thanks for the reivew.

I think we've been drop this rule[1] for quite a long time :)

[1]https://www.phoronix.com/news/Linux-Kernel-Deprecates-80-Col

> rockchip->supports_clkreq = of_property_read_bool(pdev->dev.of_node,
>                            "supports-clkreq");
> 
> I have no doubts about the rest.
> 
> Reviewed-by: Hans Zhang <hans.zhang@cixtech.com>
> 
> 
> Best regards,
> Hans
> 
>> +
>>          return 0;
>>   }
>>
>> -- 
>> 2.7.4
>>
>>
> 
>