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From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: sashiko-reviews@lists.linux.dev
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH 07/15] perf/x86/intel: Reject SAMPLE_READ for no-counter-snapshot ACR events
Date: Tue, 29 Sep 2026 14:08:49 +0800	[thread overview]
Message-ID: <1827c1cc-a543-4a27-afb5-ccef49493055@linux.intel.com> (raw)
In-Reply-To: <20260928080451.9139A1F00893@smtp.kernel.org>


On 9/28/2026 4:04 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Medium] perf/x86: Validation bypass for SAMPLE_READ on ACR events via software events
> --
>
> commit cc3bcd9a57c859b5993ae9c14bd06faec36a3c33
> Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
>
> perf/x86/intel: Reject SAMPLE_READ for no-counter-snapshot ACR events
>
> This commit restricts the use of PERF_SAMPLE_READ for Auto Counter Reload (ACR) 
> events to prevent perf from reporting invalid counts. It ensures that 
> SAMPLE_READ is only permitted for PEBS-backed ACR events with counter snapshot 
> support, as non-PEBS events can be auto-reloaded before software reads them.
>
>> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
>> index 377ff39124206..3fc3795534bf7 100644
>> --- a/arch/x86/events/intel/core.c
>> +++ b/arch/x86/events/intel/core.c
> [ ... ]
>
>> @@ -5184,6 +5239,10 @@ static int intel_pmu_hw_config(struct perf_event *event)
>>  		if (hweight64(cause_mask) > hweight64(hybrid(pmu, acr_cause_mask64)) ||
>>  		    num > hweight64(hybrid(event->pmu, acr_cntr_mask64)))
>>  			return -EINVAL;
>> +
>> +		if (!intel_pmu_allow_acr_sample_read(event, has_sample_read))
>> +			return -EINVAL;
>> +
> [Severity: Medium]
> Does this validation fully prevent PERF_SAMPLE_READ from being applied to ACR
> groups?
>
> Because this check is inside intel_pmu_hw_config(), it is evaluated when the
> x86 event is initialized. If a user creates an ACR hardware event group
> initially without PERF_SAMPLE_READ, it will successfully pass this check.
>
> What happens if the user subsequently creates a Software PMU event (like a
> dummy tracepoint) with PERF_SAMPLE_READ set, and attaches it to the existing
> ACR hardware group using the leader's group_fd?
>
> Since perf_event_open() allows software events to be attached to hardware
> groups without re-invoking the hardware PMU's validation callbacks for
> existing members, it appears intel_pmu_hw_config() won't be re-evaluated
> for the hardware events. 
>
> When the appended software event overflows, won't perf_output_read_group()
> read all siblings and still capture the imprecise auto-reloaded values of the
> ACR hardware counters?

Yes, it's a real risk. But it's hard to implement the check for last
software event in current framework. If the last event in the group is a
software event, then intel_pmu_hw_config() won't be involved to validate
the software event.

I suppose this could be just a corner case, we may leave this as a known
issue. Thanks.



>
>>  		/*
>>  		 * In the second round, apply the counter-constraints for
>>  		 * the events which can cause other events reload.

  reply	other threads:[~2026-09-29  6:08 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-28  7:42 [PATCH 00/15] perf/x86: Fix sampling bugs and relax slots-event grouping Dapeng Mi
2026-09-28  7:42 ` [PATCH 01/15] perf/x86/intel: Guard leader sibling walk on nr_siblings Dapeng Mi
2026-09-28  8:00   ` sashiko-bot
2026-09-28  7:42 ` [PATCH 02/15] perf/x86/intel: Reset active_fixed_ctrl_val on CPU teardown Dapeng Mi
2026-09-28  8:02   ` sashiko-bot
2026-09-28  7:42 ` [PATCH 03/15] perf/x86/intel: Reset active_pebs_data_cfg " Dapeng Mi
2026-09-28  8:07   ` sashiko-bot
2026-09-28  7:42 ` [PATCH 04/15] perf/x86/intel: Reset cached acr_cfg_b[] and cfg_c_val[] " Dapeng Mi
2026-09-28  8:01   ` sashiko-bot
2026-09-28  7:42 ` [PATCH 05/15] perf/x86/intel: Pass correct PEBS counter mask to no-drain update path Dapeng Mi
2026-09-28  7:58   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 06/15] perf/x86/intel: Limit PEBS counter iteration to valid array bounds Dapeng Mi
2026-09-28  8:00   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 07/15] perf/x86/intel: Reject SAMPLE_READ for no-counter-snapshot ACR events Dapeng Mi
2026-09-28  8:04   ` sashiko-bot
2026-09-29  6:08     ` Mi, Dapeng [this message]
2026-09-29 19:02   ` Falcon, Thomas
2026-09-30  1:12     ` Mi, Dapeng
2026-09-28  7:43 ` [PATCH 08/15] perf/x86/intel: Fix stale PEBS count without counter-group support Dapeng Mi
2026-09-28  8:02   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 09/15] perf/x86/intel: Refactor intel_pmu_drain_arch_pebs() Dapeng Mi
2026-09-28  7:57   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 10/15] perf/x86/intel: Refactor intel_pmu_drain_pebs_icl() Dapeng Mi
2026-09-28  7:59   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 11/15] perf/x86/intel: Fix invalid PEBS counts with counter-group support Dapeng Mi
2026-09-28  8:00   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 12/15] perf/x86/intel: Make ACR static_call update architectural Dapeng Mi
2026-09-28  8:02   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 13/15] perf/x86: Validate event type before topdown/mem-loads classification Dapeng Mi
2026-09-28  8:01   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 14/15] perf/core: Add event_caps dependency flags Dapeng Mi
2026-09-28  8:05   ` sashiko-bot
2026-09-29  6:34     ` Mi, Dapeng
2026-09-28  7:43 ` [PATCH 15/15] perf/x86/intel: Allow Topdown metrics with a non-leader slots event Dapeng Mi
2026-09-28  8:12   ` sashiko-bot
2026-09-29  7:04     ` Mi, Dapeng

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