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From: "Mi, Dapeng" <dapeng1.mi@linux.intel.com>
To: sashiko-reviews@lists.linux.dev
Cc: linux-perf-users@vger.kernel.org
Subject: Re: [PATCH 15/15] perf/x86/intel: Allow Topdown metrics with a non-leader slots event
Date: Tue, 29 Sep 2026 15:04:07 +0800	[thread overview]
Message-ID: <863010a8-1f71-4b87-8ae9-1c271b7e139e@linux.intel.com> (raw)
In-Reply-To: <20260928081227.314C71F000FF@smtp.kernel.org>


On 9/28/2026 4:12 PM, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
> - [High] perf: lockless sibling traversal and modification in intel_pmu_hw_config()
> - [Medium] perf: state leak on active slots event if metric event allocation fails
> --
>
> commit 35318b4bb32158e6a24c6de2f1ef286a1ed4b438
> Author: Dapeng Mi <dapeng1.mi@linux.intel.com>
> Subject: perf/x86/intel: Allow Topdown metrics with a non-leader slots event
>
> This commit relaxes the requirement for the slots event to be the group leader
> for Topdown metrics, allowing metric events to validate constraints against a
> valid slots sibling instead. It incrementally validates groups and sets
> reliance capabilities so detaching a non-leader slots event triggers dependent
> metric events into an error state.
>
>> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
>> index 6cc1462c9c82d..9025f29f625d4 100644
>> --- a/arch/x86/events/intel/core.c
>> +++ b/arch/x86/events/intel/core.c
> [ ... ]
>> @@ -5300,30 +5300,53 @@ static int intel_pmu_hw_config(struct perf_event *event)
>>  
>>  		if (is_available_metric_event(event)) {
>>  			struct perf_event *leader = event->group_leader;
>> +			struct perf_event *slots = NULL;
>> +			struct perf_event *sibling;
>>  
>>  			/* The metric events don't support sampling. */
>>  			if (is_sampling_event(event))
>>  				return -EINVAL;
>>  
>> -			/* The metric events require a slots group leader. */
>> -			if (!is_slots_event(leader))
>> +			/*
>> +			 * intel_pmu_hw_config() cannot tell whether the current
>> +			 * event is the last one in the group. Require the slots
>> +			 * event to appear before all metric events.
>> +			 */
>> +			if (is_slots_event(leader)) {
>> +				slots = leader;
>> +			} else if (leader->nr_siblings) {
>> +				for_each_sibling_event(sibling, leader) {
> [Severity: High]
> When a user calls perf_event_open() to add a metric event to an already
> active hardware group, this is executed without holding the group leader's
> ctx->mutex.
>
> Does traversing the sibling_list without the context lock here cause a data
> race? A concurrent thread closing a sibling file descriptor triggers
> perf_group_detach(), which mutates the list and could lead to list
> corruption or a use-after-free.
>
> Additionally, since for_each_sibling_event() invokes
> lockdep_assert_event_ctx(), will this trigger a WARN_ON_ONCE because the
> required lock is not held?

No, the ctx->mutex is held for sibling events. perf_event_ctx_lock_nested()
would acquire ctx->mutex before calling pmu->event_init().


>
>> +					if (is_slots_event(sibling)) {
>> +						slots = sibling;
>> +						break;
>> +					}
>> +				}
>> +			}
> [ ... ]
>> +			if (slots == leader) {
>> +				event->event_caps |= PERF_EV_CAP_SIBLING;
>> +			} else {
>> +				slots->event_caps |= PERF_EV_CAP_RELIED_ON;
>> +				event->event_caps |= PERF_EV_CAP_RELIANT;
>> +			}
>>  			/*
>>  			 * Only once we have a METRICs sibling do we
>>  			 * need TopDown magic.
>>  			 */
>> -			leader->hw.flags |= PERF_X86_EVENT_TOPDOWN;
>> -			event->hw.flags  |= PERF_X86_EVENT_TOPDOWN;
>> +			slots->hw.flags |= PERF_X86_EVENT_TOPDOWN;
> [Severity: High]
> Does locklessly modifying the active slots event's event_caps and hw.flags
> cause issues for running events? Setting PERF_X86_EVENT_TOPDOWN on a
> running event changes its NMI read path to intel_update_topdown_event.
> Because its saved_slots was uninitialized (0), this could subtract 0 from
> the raw MSR value, resulting in double-counting the event.

It's just a risk in theory, it should never really happen. slots event and
topdown metric events must be in a group and all events should be enabled
and scheduled at the same time, so it's impossible that we see a slots is
running but the topdown metric events in same group are still in creation.


>
> [Severity: Medium]
> What happens to these modifications if the new metric event allocation
> fails later on (for instance, in perf_allow_cpu(),
> security_perf_event_alloc(), or perf_cgroup_connect())?
>
> Since there is no rollback mechanism in the error path to restore the slots
> event, it appears to permanently leak state. Being incorrectly flagged with
> PERF_EV_CAP_RELIED_ON and PERF_X86_EVENT_TOPDOWN permanently alters its
> NMI read path and breaks its sampling capabilities, even though the
> dependent metric event was never successfully created.

If an event member fails to pass the validation, but the other members in
the group still could success, we should not roll back the setting if a
member fails to pass the validation. 

Thanks.


>

      reply	other threads:[~2026-09-29  7:04 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-28  7:42 [PATCH 00/15] perf/x86: Fix sampling bugs and relax slots-event grouping Dapeng Mi
2026-09-28  7:42 ` [PATCH 01/15] perf/x86/intel: Guard leader sibling walk on nr_siblings Dapeng Mi
2026-09-28  8:00   ` sashiko-bot
2026-09-28  7:42 ` [PATCH 02/15] perf/x86/intel: Reset active_fixed_ctrl_val on CPU teardown Dapeng Mi
2026-09-28  8:02   ` sashiko-bot
2026-09-28  7:42 ` [PATCH 03/15] perf/x86/intel: Reset active_pebs_data_cfg " Dapeng Mi
2026-09-28  8:07   ` sashiko-bot
2026-09-28  7:42 ` [PATCH 04/15] perf/x86/intel: Reset cached acr_cfg_b[] and cfg_c_val[] " Dapeng Mi
2026-09-28  8:01   ` sashiko-bot
2026-09-28  7:42 ` [PATCH 05/15] perf/x86/intel: Pass correct PEBS counter mask to no-drain update path Dapeng Mi
2026-09-28  7:58   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 06/15] perf/x86/intel: Limit PEBS counter iteration to valid array bounds Dapeng Mi
2026-09-28  8:00   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 07/15] perf/x86/intel: Reject SAMPLE_READ for no-counter-snapshot ACR events Dapeng Mi
2026-09-28  8:04   ` sashiko-bot
2026-09-29  6:08     ` Mi, Dapeng
2026-09-29 19:02   ` Falcon, Thomas
2026-09-30  1:12     ` Mi, Dapeng
2026-09-28  7:43 ` [PATCH 08/15] perf/x86/intel: Fix stale PEBS count without counter-group support Dapeng Mi
2026-09-28  8:02   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 09/15] perf/x86/intel: Refactor intel_pmu_drain_arch_pebs() Dapeng Mi
2026-09-28  7:57   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 10/15] perf/x86/intel: Refactor intel_pmu_drain_pebs_icl() Dapeng Mi
2026-09-28  7:59   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 11/15] perf/x86/intel: Fix invalid PEBS counts with counter-group support Dapeng Mi
2026-09-28  8:00   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 12/15] perf/x86/intel: Make ACR static_call update architectural Dapeng Mi
2026-09-28  8:02   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 13/15] perf/x86: Validate event type before topdown/mem-loads classification Dapeng Mi
2026-09-28  8:01   ` sashiko-bot
2026-09-28  7:43 ` [PATCH 14/15] perf/core: Add event_caps dependency flags Dapeng Mi
2026-09-28  8:05   ` sashiko-bot
2026-09-29  6:34     ` Mi, Dapeng
2026-09-28  7:43 ` [PATCH 15/15] perf/x86/intel: Allow Topdown metrics with a non-leader slots event Dapeng Mi
2026-09-28  8:12   ` sashiko-bot
2026-09-29  7:04     ` Mi, Dapeng [this message]

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