From: sashiko-bot@kernel.org
To: "Florian Fainelli" <f.fainelli@gmail.com>
Cc: "open list:PERFORMANCE EVENTS SUBSYSTEM"
<linux-perf-users@vger.kernel.org>
Subject: Re: [PATCH v2 1/3] MIPS: SiByte: Wire up the CPU interrupt controller
Date: Fri, 13 Nov 2026 23:53:20 +0000 [thread overview]
Message-ID: <sashiko-outbox-213881@kernel.org> (raw)
In-Reply-To: <20261113233358.538698-2-f.fainelli@gmail.com>
> Initialize the MIPS CPU interrupt controller on SB1250 and BCM1480 so
> CPU-local interrupts have a configured irq_chip and handler. Reserve IRQs
> 128 through 135 above both interrupt mapper ranges, and dispatch BCM1480
> IP7 through the CPU controller as SB1250 already does.
>
> This provides the CPU-local IP7 interrupt needed by the SB1 performance
> counters without overlapping the SiByte interrupt mapper IRQ numbers.
>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Sashiko has reviewed this patch and found no issues.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261113233358.538698-1-f.fainelli@gmail.com?part=1
next prev parent reply other threads:[~2026-11-13 23:53 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 23:33 [PATCH v2 0/3] MIPS: SiByte: Add HW PMU support Florian Fainelli
2026-11-13 23:33 ` [PATCH v2 1/3] MIPS: SiByte: Wire up the CPU interrupt controller Florian Fainelli
2026-11-13 23:53 ` sashiko-bot [this message]
2026-11-13 23:33 ` [PATCH v2 2/3] MIPS: perf: Add SB1 userspace callchain unwinding Florian Fainelli
2026-11-13 23:47 ` sashiko-bot
2026-11-13 23:33 ` [PATCH v2 3/3] MIPS: perf: Add SB1 and SB1A performance counter support Florian Fainelli
2026-11-13 23:54 ` sashiko-bot
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