From: sashiko-bot@kernel.org
To: "Florian Fainelli" <f.fainelli@gmail.com>
Cc: "open list:PERFORMANCE EVENTS SUBSYSTEM"
<linux-perf-users@vger.kernel.org>
Subject: Re: [PATCH v2 3/3] MIPS: perf: Add SB1 and SB1A performance counter support
Date: Fri, 13 Nov 2026 23:54:22 +0000 [thread overview]
Message-ID: <sashiko-outbox-213885@kernel.org> (raw)
In-Reply-To: <20261113233358.538698-4-f.fainelli@gmail.com>
Thank you for your contribution! Sashiko AI review found 1 potential
issue to consider:
- [Low] MIPS: perf: preemptible smp_processor_id() call in is_sb1_pmu()
--
commit f968ced28e6948da3887ac13c02f7c72caf1a26e
Author: Florian Fainelli <f.fainelli@gmail.com>
MIPS: perf: Add SB1 and SB1A performance counter support
This commit adds performance counter support for SB1 and SB1A CPUs to the
MIPS PMU driver, along with documentation and CPU hotplug state handling.
> diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
> index 196a070349b09..7a212d4757a0a 100644
> --- a/arch/mips/kernel/perf_event_mipsxx.c
> +++ b/arch/mips/kernel/perf_event_mipsxx.c
[ ... ]
> @@ -93,6 +102,12 @@ struct mips_pmu {
> static int counter_bits;
> static struct mips_pmu mipspmu;
>
> +static bool is_sb1_pmu(void)
> +{
> + return current_cpu_type() == CPU_SB1 ||
> + current_cpu_type() == CPU_SB1A;
> +}
[Severity: Low]
Should is_sb1_pmu() use boot_cpu_type() (like get_loongson3_pmu_type() in
this file) instead of current_cpu_type()?
current_cpu_type() reads current_cpu_data.cputype, which expands to
cpu_data[smp_processor_id()].cputype. Because is_sb1_pmu() is called from
preemptible process context in paths such as mipspmu_event_init(), opening
or closing a perf event from a task that is not pinned to a single CPU
triggers a debug_smp_processor_id() warning when CONFIG_DEBUG_PREEMPT is
enabled.
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261113233358.538698-1-f.fainelli@gmail.com?part=3
prev parent reply other threads:[~2026-11-13 23:54 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 23:33 [PATCH v2 0/3] MIPS: SiByte: Add HW PMU support Florian Fainelli
2026-11-13 23:33 ` [PATCH v2 1/3] MIPS: SiByte: Wire up the CPU interrupt controller Florian Fainelli
2026-11-13 23:53 ` sashiko-bot
2026-11-13 23:33 ` [PATCH v2 2/3] MIPS: perf: Add SB1 userspace callchain unwinding Florian Fainelli
2026-11-13 23:47 ` sashiko-bot
2026-11-13 23:33 ` [PATCH v2 3/3] MIPS: perf: Add SB1 and SB1A performance counter support Florian Fainelli
2026-11-13 23:54 ` sashiko-bot [this message]
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