From: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
To: geocausa@gmail.com, Bryan O'Donoghue <bod@kernel.org>,
Vinod Koul <vkoul@kernel.org>, David Heidelberg <david@ixit.cz>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
Loic Poulain <loic.poulain@oss.qualcomm.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Vikram Sharma <vikram.sharma@oss.qualcomm.com>,
Suresh Vankadara <svankada@qti.qualcomm.com>,
tjose@qti.qualcomm.com,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Manivannan Sadhasivam <mani@kernel.org>,
linux-phy@lists.infradead.org, linux-media@vger.kernel.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH RFC v2 4/4] phy: qcom-mipi-csi2: Add C-PHY support for X1E80100
Date: Fri, 16 Oct 2026 17:05:37 +0530 [thread overview]
Message-ID: <010f8a27-e058-4c8b-8681-24df30c29853@oss.qualcomm.com> (raw)
In-Reply-To: <20261016-x1e-cphy-rfc-v2-4-377654253193@gmail.com>
On 16-10-2026 16:27, George Neacsu via B4 Relay wrote:
> + {.reg_addr = 0x0a54, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0a40, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0a60, .reg_data = 0xa8, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0a84, .reg_data = 0x00, .param_type = CSIPHY_DEFAULT_PARAMS},
> + {.reg_addr = 0x0a90, .reg_data = 0x02, .param_type = CSIPHY_DEFAULT_PARAMS},
> +
> + /* csiphy_reset_exit_reg_2_1_2, 3PH */
> + {.reg_addr = 0x1000, .reg_data = 0x0e, .delay_us = 3048,
> + .param_type = CSIPHY_DEFAULT_PARAMS},
> +};
> +
I checked the register settings and they look good to me.
Can we write the delay value in hex as well, to keep the table
formatting consistent.
--
Regards,
Nihal Kumar Gupta
--
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy
next prev parent reply other threads:[~2026-10-16 11:35 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <K9h_NQSPlrzzoVDIqqNPGT6KDZNScVi2mlqy6yNs8VOOS_I4KXf0QLy4k3Cwo2qKhnfL_qUK5wnY4h6wX24L4A==@protonmail.internalid>
2026-10-16 10:57 ` [PATCH RFC v2 0/4] phy: qcom-mipi-csi2: C-PHY for X1E80100 George Neacsu via B4 Relay
2026-10-16 10:57 ` [PATCH RFC v2 1/4] phy: Add MIPI C-PHY mode and configuration options George Neacsu via B4 Relay
2026-10-16 11:04 ` sashiko-bot
2026-10-16 11:35 ` Nihal Kumar Gupta
2026-10-16 14:16 ` Loic Poulain
2026-10-16 10:57 ` [PATCH RFC v2 2/4] phy: Add MIPI C-PHY configuration helpers George Neacsu via B4 Relay
2026-10-16 11:06 ` Bryan O'Donoghue
2026-10-16 10:57 ` [PATCH RFC v2 3/4] phy: qcom-mipi-csi2: Rename the D-PHY init sequence George Neacsu via B4 Relay
2026-10-16 11:07 ` Bryan O'Donoghue
2026-10-16 10:57 ` [PATCH RFC v2 4/4] phy: qcom-mipi-csi2: Add C-PHY support for X1E80100 George Neacsu via B4 Relay
2026-10-16 11:15 ` Bryan O'Donoghue
2026-10-16 11:35 ` Nihal Kumar Gupta [this message]
2026-10-16 12:05 ` Konrad Dybcio
2026-10-16 12:25 ` Nihal Kumar Gupta
2026-10-16 12:24 ` David Heidelberg
2026-10-16 11:02 ` [PATCH RFC v2 0/4] phy: qcom-mipi-csi2: C-PHY " Bryan O'Donoghue
2026-10-16 11:32 ` George Neacsu
2026-10-16 13:27 ` Bryan O'Donoghue
2026-10-16 14:55 ` George Neacsu
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