Re: [PATCH 3/4] arm64: dts: qcom: ipq5424: Add PCIe PHYs and controller nodes

[Manikanta Mylavarapu <quic_mmanikan@quicinc.com>]

On 12/13/2024 8:36 PM, Konrad Dybcio wrote:
> On 13.12.2024 2:49 PM, Manikanta Mylavarapu wrote:
>> Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
>> found on IPQ5424 platform. The PCIe0 & PCIe1 are 1-lane Gen3
>> host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
>>
>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
>> ---
>>  arch/arm64/boot/dts/qcom/ipq5424.dtsi | 482 +++++++++++++++++++++++++-
>>  1 file changed, 477 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> index 5e219f900412..ade512bcb180 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi
>> @@ -9,6 +9,7 @@
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>  #include <dt-bindings/clock/qcom,ipq5424-gcc.h>
>>  #include <dt-bindings/reset/qcom,ipq5424-gcc.h>
>> +#include <dt-bindings/interconnect/qcom,ipq5424.h>
>>  #include <dt-bindings/gpio/gpio.h>
>>  
>>  / {
>> @@ -143,7 +144,99 @@ soc@0 {
>>  		compatible = "simple-bus";
>>  		#address-cells = <2>;
>>  		#size-cells = <2>;
>> -		ranges = <0 0 0 0 0x10 0>;
>> +		ranges = <0 0 0 0 0x0 0xffffffff>;
> 
> This must be a separate change, with a clear explanation
> 
>> +
>> +		pcie0_phy: phy@84000 {
>> +			compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy",
>> +				     "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>> +			reg = <0 0x00084000 0 0x2000>;
>> +			clocks = <&gcc GCC_PCIE0_AUX_CLK>,
>> +				 <&gcc GCC_PCIE0_AHB_CLK>,
>> +				 <&gcc GCC_PCIE0_PIPE_CLK>;
>> +			clock-names = "aux", "cfg_ahb", "pipe";
>> +
>> +			assigned-clocks = <&gcc GCC_PCIE0_AUX_CLK>;
>> +			assigned-clock-rates = <20000000>;
>> +
>> +			resets = <&gcc GCC_PCIE0_PHY_BCR>,
>> +				 <&gcc GCC_PCIE0PHY_PHY_BCR>;
>> +			reset-names = "phy", "common";
>> +
>> +			#clock-cells = <0>;
>> +			clock-output-names = "gcc_pcie0_pipe_clk_src";
>> +
>> +			#phy-cells = <0>;
>> +			status = "disabled";
>> +		};
>> +
>> +		pcie1_phy: phy@8c000 {
>> +			compatible = "qcom,ipq5424-qmp-gen3x1-pcie-phy",
>> +				     "qcom,ipq9574-qmp-gen3x1-pcie-phy";
>> +			reg = <0 0x0008c000 0 0x2000>;
>> +			clocks = <&gcc GCC_PCIE1_AUX_CLK>,
>> +				 <&gcc GCC_PCIE1_AHB_CLK>,
>> +				 <&gcc GCC_PCIE1_PIPE_CLK>;
>> +			clock-names = "aux", "cfg_ahb", "pipe";
>> +
>> +			assigned-clocks = <&gcc GCC_PCIE1_AUX_CLK>;
>> +			assigned-clock-rates = <20000000>;
>> +
>> +			resets = <&gcc GCC_PCIE1_PHY_BCR>,
>> +				 <&gcc GCC_PCIE1PHY_PHY_BCR>;
>> +			reset-names = "phy", "common";
>> +
>> +			#clock-cells = <0>;
>> +			clock-output-names = "gcc_pcie1_pipe_clk_src";
>> +
>> +			#phy-cells = <0>;
>> +			status = "disabled";
>> +		};
>> +
>> +		pcie2_phy: phy@f4000 {
>> +			compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy",
>> +				     "qcom,ipq9574-qmp-gen3x2-pcie-phy";
>> +			reg = <0 0x000f4000 0 0x2000>;
>> +			clocks = <&gcc GCC_PCIE2_AUX_CLK>,
>> +				 <&gcc GCC_PCIE2_AHB_CLK>,
>> +				 <&gcc GCC_PCIE2_PIPE_CLK>;
>> +			clock-names = "aux", "cfg_ahb", "pipe";
>> +
>> +			assigned-clocks = <&gcc GCC_PCIE2_AUX_CLK>;
>> +			assigned-clock-rates = <20000000>;
>> +
>> +			resets = <&gcc GCC_PCIE2_PHY_BCR>,
>> +				 <&gcc GCC_PCIE2PHY_PHY_BCR>;
>> +			reset-names = "phy", "common";
>> +
>> +			#clock-cells = <0>;
>> +			clock-output-names = "gcc_pcie2_pipe_clk_src";
>> +
>> +			#phy-cells = <0>;
>> +			status = "disabled";
>> +		};
>> +
>> +		pcie3_phy: phy@fc000 {
>> +			compatible = "qcom,ipq5424-qmp-gen3x2-pcie-phy",
>> +				     "qcom,ipq9574-qmp-gen3x2-pcie-phy";
>> +			reg = <0 0x000fc000 0 0x2000>;
>> +			clocks = <&gcc GCC_PCIE3_AUX_CLK>,
>> +				 <&gcc GCC_PCIE3_AHB_CLK>,
>> +				 <&gcc GCC_PCIE3_PIPE_CLK>;
>> +			clock-names = "aux", "cfg_ahb", "pipe";
>> +
>> +			assigned-clocks = <&gcc GCC_PCIE3_AUX_CLK>;
>> +			assigned-clock-rates = <20000000>;
>> +
>> +			resets = <&gcc GCC_PCIE3_PHY_BCR>,
>> +				 <&gcc GCC_PCIE3PHY_PHY_BCR>;
>> +			reset-names = "phy", "common";
>> +
>> +			#clock-cells = <0>;
>> +			clock-output-names = "gcc_pcie3_pipe_clk_src";
>> +
>> +			#phy-cells = <0>;
>> +			status = "disabled";
>> +		};
>>  
>>  		tlmm: pinctrl@1000000 {
>>  			compatible = "qcom,ipq5424-tlmm";
>> @@ -168,11 +261,11 @@ gcc: clock-controller@1800000 {
>>  			reg = <0 0x01800000 0 0x40000>;
>>  			clocks = <&xo_board>,
>>  				 <&sleep_clk>,
>> +				 <&pcie0_phy>,
>> +				 <&pcie1_phy>,
>>  				 <0>,
> 
> This leftover zero needs to be removed too, currently the wrong
> clocks are used as parents
> 

Hi Konrad,

The '<0>' entry is for "USB PCIE wrapper pipe clock source".
And, will update the pcie entries as follows
	<&pcie0_phy GCC_PCIE0_PIPE_CLK>
	<&pcie1_phy GCC_PCIE1_PIPE_CLK>
	<&pcie2_phy GCC_PCIE2_PIPE_CLK>
	<&pcie3_phy GCC_PCIE3_PIPE_CLK>

Please correct me if i am wrong.

Thanks & Regards,
Manikanta.

>> -				 <0>,
>> -				 <0>,
>> -				 <0>,
>> -				 <0>;
>> +				 <&pcie2_phy>,
>> +				 <&pcie3_phy>;
>>  			#clock-cells = <1>;
>>  			#reset-cells = <1>;
>>  			#interconnect-cells = <1>;
>> @@ -292,6 +385,385 @@ frame@f42d000 {
>>  			};
>>  		};
>>  

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