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From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>,
	Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com,
	manivannan.sadhasivam@linaro.org, robh@kernel.org,
	krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org,
	kishon@kernel.org, andersson@kernel.org, konradybcio@kernel.org,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-phy@lists.infradead.org
Cc: quic_srichara@quicinc.com, quic_varada@quicinc.com
Subject: Re: [PATCH 3/4] arm64: dts: qcom: ipq5424: Add PCIe PHYs and controller nodes
Date: Fri, 20 Dec 2024 10:48:40 +0100	[thread overview]
Message-ID: <71d2135f-664a-465d-bc1f-051cc07c8537@oss.qualcomm.com> (raw)
In-Reply-To: <08fbde92-a827-4270-a143-cca56a274e6c@quicinc.com>

On 20.12.2024 7:42 AM, Manikanta Mylavarapu wrote:
> 
> 
> On 12/13/2024 8:36 PM, Konrad Dybcio wrote:
>> On 13.12.2024 2:49 PM, Manikanta Mylavarapu wrote:
>>> Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
>>> found on IPQ5424 platform. The PCIe0 & PCIe1 are 1-lane Gen3
>>> host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.
>>>
>>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
>>> ---

[...]

>>>  		tlmm: pinctrl@1000000 {
>>>  			compatible = "qcom,ipq5424-tlmm";
>>> @@ -168,11 +261,11 @@ gcc: clock-controller@1800000 {
>>>  			reg = <0 0x01800000 0 0x40000>;
>>>  			clocks = <&xo_board>,
>>>  				 <&sleep_clk>,
>>> +				 <&pcie0_phy>,
>>> +				 <&pcie1_phy>,
>>>  				 <0>,
>>
>> This leftover zero needs to be removed too, currently the wrong
>> clocks are used as parents
>>
> 
> Hi Konrad,
> 
> The '<0>' entry is for "USB PCIE wrapper pipe clock source".
> And, will update the pcie entries as follows
> 	<&pcie0_phy GCC_PCIE0_PIPE_CLK>
> 	<&pcie1_phy GCC_PCIE1_PIPE_CLK>
> 	<&pcie2_phy GCC_PCIE2_PIPE_CLK>
> 	<&pcie3_phy GCC_PCIE3_PIPE_CLK>
> 
> Please correct me if i am wrong.

The order of these is fixed by the first enum in
drivers/clk/qcom/gcc-ipq5424.c. The <0> entry must be at the end of
the clocks list for it to do what you want it to.

Konrad

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  reply	other threads:[~2024-12-20  9:48 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-13 13:49 [PATCH 0/4] Add PCIe support for IPQ5424 Manikanta Mylavarapu
2024-12-13 13:49 ` [PATCH 1/4] dt-bindings: PCI: qcom: Document the IPQ5424 PCIe controller Manikanta Mylavarapu
2024-12-17  7:26   ` Krzysztof Kozlowski
2025-01-15 11:38   ` Krzysztof Wilczyński
2024-12-13 13:49 ` [PATCH 2/4] dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ5424 QMP PCIe PHYs Manikanta Mylavarapu
2024-12-17  7:27   ` Krzysztof Kozlowski
2024-12-13 13:49 ` [PATCH 3/4] arm64: dts: qcom: ipq5424: Add PCIe PHYs and controller nodes Manikanta Mylavarapu
2024-12-13 15:06   ` Konrad Dybcio
2024-12-20  6:09     ` Manikanta Mylavarapu
2024-12-20  6:42     ` Manikanta Mylavarapu
2024-12-20  9:48       ` Konrad Dybcio [this message]
2024-12-20 11:28         ` Manikanta Mylavarapu
2024-12-13 13:49 ` [PATCH 4/4] arm64: dts: qcom: ipq5424: Enable PCIe PHYs and controllers Manikanta Mylavarapu
2024-12-13 15:07   ` Konrad Dybcio
2025-01-02  6:08     ` Manikanta Mylavarapu
2025-01-03  6:52   ` Varadarajan Narayanan
2025-01-15  6:10     ` Manikanta Mylavarapu
2024-12-24 15:25 ` (subset) [PATCH 0/4] Add PCIe support for IPQ5424 Vinod Koul

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