[PATCH v5 0/2] phy: qcom: qmp-pcie: Add PCIe PHY no_csr reset support

[PATCH v5 0/2] phy: qcom: qmp-pcie: Add PCIe PHY no_csr reset support

[Wenbin Yao]

The series aims to skip phy register programming and drive PCIe PHY with
register setting programmed in bootloader by simply toggling no_csr reset,
which once togglled, PHY hardware will be reset while PHY registers are
retained.

First, determine whether PHY setting can be skipped by checking
QPHY_START_CTRL register and the existence of nocsr reset. If it is
programmed and no_csr reset is supported, do no_csr reset and skip BCR
reset which will reset entire PHY.

This series also remove has_nocsr_reset flag in qmp_phy_cfg structure and
decide whether the PHY supports nocsr reset by checking the existence of
nocsr reset in device tree.

The series are tested on X1E80100-QCP and HDK8550.

The commit messages of this patchset have been modified based on comments
and suggestions.

Changes in v5:
- Add a check whether the init sequences are exist if the PHY needs to be
  initialized to Patch 2/2.
- Link to v4: https://lore.kernel.org/all/20250220102253.755116-1-quic_wenbyao@quicinc.com/ 

Changes in v4:
- Add Philipp's Reviewed-by tag to Patch 1/2.
- Use PHY instead of phy in comments in Patch 2/2.
- Use "if (qmp->nocsr_reset)" instead of "if (!qmp->nocsr_reset)" in
  function qmp_pcie_exit for readability in Patch 2/2.
- Use goto statements in function qmp_pcie_power_on and qmp_pcie_power_off
  for readability in Patch 2/2.
- Refine the comment of why not checking qmp->skip_init when reset PHY in
  function qmp_pcie_power_off in Patch 2/2.
- Link to v3: https://lore.kernel.org/all/20250214104539.281846-1-quic_wenbyao@quicinc.com/

Changes in v3:
- Replace devm_reset_control_get_exclusive with
  devm_reset_control_get_optional_exclusive when get phy_nocsr reset
  control in Patch 1/2.
- Do not ignore -EINVAL when get phy_nocsr reset control in Patch 1/2.
- Replace phy_initialized with skip_init in struct qmp_pcie in Patch 2/2.
- Add a comment to why not check qmp->skip_init in function
  qmp_pcie_power_off in Patch 2/2.
- Link to v2: https://lore.kernel.org/all/20250211094231.1813558-1-quic_wenbyao@quicinc.com/

Changes in v2:
- Add Abel's and Manivannan's Reviewed-by tag to Patch 1/2.
- Refine commit msg of Patch 2/2.
- Link to v1: https://lore.kernel.org/all/20250121094140.4006801-1-quic_wenbyao@quicinc.com/

Konrad Dybcio (1):
  phy: qcom: pcie: Determine has_nocsr_reset dynamically

Qiang Yu (1):
  phy: qcom: qmp-pcie: Add PHY register retention support

 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 86 +++++++++++++++++-------
 1 file changed, 63 insertions(+), 23 deletions(-)


base-commit: bcf2acd8f64b0a5783deeeb5fd70c6163ec5acd7
-- 
2.34.1


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[PATCH v5 1/2] phy: qcom: pcie: Determine has_nocsr_reset dynamically

[Wenbin Yao]

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Decide the in-driver logic based on whether the nocsr reset is present
and defer checking the appropriateness of that to dt-bindings to save
on boilerplate.

Reset controller APIs are fine consuming a nullptr, so no additional
checks are necessary there.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 17 ++++-------------
 1 file changed, 4 insertions(+), 13 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 873f2f9844c6..219266125cf2 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -2793,8 +2793,6 @@ struct qmp_phy_cfg {
 
 	bool skip_start_delay;
 
-	bool has_nocsr_reset;
-
 	/* QMP PHY pipe clock interface rate */
 	unsigned long pipe_clock_rate;
 
@@ -3685,7 +3683,6 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
 
 	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
 	.phy_status		= PHYSTATUS_4_20,
-	.has_nocsr_reset	= true,
 
 	/* 20MHz PHY AUX Clock */
 	.aux_clock_rate		= 20000000,
@@ -3718,7 +3715,6 @@ static const struct qmp_phy_cfg sm8650_qmp_gen4x2_pciephy_cfg = {
 
 	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
 	.phy_status		= PHYSTATUS_4_20,
-	.has_nocsr_reset	= true,
 
 	/* 20MHz PHY AUX Clock */
 	.aux_clock_rate		= 20000000,
@@ -3836,7 +3832,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x2_pciephy_cfg = {
 
 	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
 	.phy_status		= PHYSTATUS_4_20,
-	.has_nocsr_reset	= true,
 };
 
 static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = {
@@ -3870,7 +3865,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x4_pciephy_cfg = {
 
 	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
 	.phy_status		= PHYSTATUS_4_20,
-	.has_nocsr_reset	= true,
 };
 
 static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = {
@@ -3902,7 +3896,6 @@ static const struct qmp_phy_cfg x1e80100_qmp_gen4x8_pciephy_cfg = {
 
 	.pwrdn_ctrl		= SW_PWRDN | REFCLK_DRV_DSBL,
 	.phy_status		= PHYSTATUS_4_20,
-	.has_nocsr_reset	= true,
 };
 
 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
@@ -4203,12 +4196,10 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
 	if (ret)
 		return dev_err_probe(dev, ret, "failed to get resets\n");
 
-	if (cfg->has_nocsr_reset) {
-		qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr");
-		if (IS_ERR(qmp->nocsr_reset))
-			return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
-						"failed to get no-csr reset\n");
-	}
+	qmp->nocsr_reset = devm_reset_control_get_optional_exclusive(dev, "phy_nocsr");
+	if (IS_ERR(qmp->nocsr_reset))
+		return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
+				     "failed to get no-csr reset\n");
 
 	return 0;
 }
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[PATCH v5 2/2] phy: qcom: qmp-pcie: Add PHY register retention support

[Wenbin Yao]

From: Qiang Yu <quic_qianyu@quicinc.com>

Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the
whole PHY (hardware and register), no_csr reset only resets PHY hardware
but retains register values, which means PHY setting can be skipped during
PHY init if PCIe link is enabled in booltloader and only no_csr is toggled
after that.

Hence, determine whether the PHY has been enabled in bootloader by
verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is
available, skip BCR reset and PHY register setting to establish the PCIe
link with bootloader - programmed PHY settings.

Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
---
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 69 ++++++++++++++++++++----
 1 file changed, 59 insertions(+), 10 deletions(-)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index 219266125cf2..c3642d1807e4 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -2805,6 +2805,7 @@ struct qmp_pcie {
 
 	const struct qmp_phy_cfg *cfg;
 	bool tcsr_4ln_config;
+	bool skip_init;
 
 	void __iomem *serdes;
 	void __iomem *pcs;
@@ -3976,18 +3977,38 @@ static int qmp_pcie_init(struct phy *phy)
 {
 	struct qmp_pcie *qmp = phy_get_drvdata(phy);
 	const struct qmp_phy_cfg *cfg = qmp->cfg;
+	void __iomem *pcs = qmp->pcs;
+	bool phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL]));
 	int ret;
 
+	qmp->skip_init = qmp->nocsr_reset && phy_initialized;
+	/*
+	 * We need to check the existence of init sequences in two cases:
+	 * 1. The PHY doesn't support no_csr reset.
+	 * 2. The PHY supports no_csr reset but isn't initialized by bootloader.
+	 * As we can't skip init in these two cases.
+	 */
+	if (!qmp->skip_init && !cfg->tbls.serdes_num) {
+		dev_err(qmp->dev, "no init sequences are available\n");
+		return -EINVAL;
+	}
+
 	ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
 	if (ret) {
 		dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
 		return ret;
 	}
 
-	ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
-	if (ret) {
-		dev_err(qmp->dev, "reset assert failed\n");
-		goto err_disable_regulators;
+	/*
+	 * Toggle BCR reset for PHY that doesn't support no_csr reset or has not
+	 * been initialized.
+	 */
+	if (!qmp->skip_init) {
+		ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
+		if (ret) {
+			dev_err(qmp->dev, "reset assert failed\n");
+			goto err_disable_regulators;
+		}
 	}
 
 	ret = reset_control_assert(qmp->nocsr_reset);
@@ -3998,10 +4019,12 @@ static int qmp_pcie_init(struct phy *phy)
 
 	usleep_range(200, 300);
 
-	ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
-	if (ret) {
-		dev_err(qmp->dev, "reset deassert failed\n");
-		goto err_assert_reset;
+	if (!qmp->skip_init) {
+		ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
+		if (ret) {
+			dev_err(qmp->dev, "reset deassert failed\n");
+			goto err_assert_reset;
+		}
 	}
 
 	ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
@@ -4011,7 +4034,8 @@ static int qmp_pcie_init(struct phy *phy)
 	return 0;
 
 err_assert_reset:
-	reset_control_bulk_assert(cfg->num_resets, qmp->resets);
+	if (!qmp->skip_init)
+		reset_control_bulk_assert(cfg->num_resets, qmp->resets);
 err_disable_regulators:
 	regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
 
@@ -4023,7 +4047,10 @@ static int qmp_pcie_exit(struct phy *phy)
 	struct qmp_pcie *qmp = phy_get_drvdata(phy);
 	const struct qmp_phy_cfg *cfg = qmp->cfg;
 
-	reset_control_bulk_assert(cfg->num_resets, qmp->resets);
+	if (qmp->nocsr_reset)
+		reset_control_assert(qmp->nocsr_reset);
+	else
+		reset_control_bulk_assert(cfg->num_resets, qmp->resets);
 
 	clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
 
@@ -4042,6 +4069,13 @@ static int qmp_pcie_power_on(struct phy *phy)
 	unsigned int mask, val;
 	int ret;
 
+	/*
+	 * Write CSR register for PHY that doesn't support no_csr reset or has not
+	 * been initialized.
+	 */
+	if (qmp->skip_init)
+		goto skip_tbls_init;
+
 	qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
 			cfg->pwrdn_ctrl);
 
@@ -4053,6 +4087,7 @@ static int qmp_pcie_power_on(struct phy *phy)
 	qmp_pcie_init_registers(qmp, &cfg->tbls);
 	qmp_pcie_init_registers(qmp, mode_tbls);
 
+skip_tbls_init:
 	ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
 	if (ret)
 		return ret;
@@ -4063,6 +4098,9 @@ static int qmp_pcie_power_on(struct phy *phy)
 		goto err_disable_pipe_clk;
 	}
 
+	if (qmp->skip_init)
+		goto skip_serdes_start;
+
 	/* Pull PHY out of reset state */
 	qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
 
@@ -4072,6 +4110,7 @@ static int qmp_pcie_power_on(struct phy *phy)
 	if (!cfg->skip_start_delay)
 		usleep_range(1000, 1200);
 
+skip_serdes_start:
 	status = pcs + cfg->regs[QPHY_PCS_STATUS];
 	mask = cfg->phy_status;
 	ret = readl_poll_timeout(status, val, !(val & mask), 200,
@@ -4096,6 +4135,15 @@ static int qmp_pcie_power_off(struct phy *phy)
 
 	clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
 
+	/*
+	 * While powering off the PHY, only qmp->nocsr_reset needs to be checked. In
+	 * this way, no matter whether the PHY settings were initially programmed by
+	 * bootloader or PHY driver itself, we can reuse them when PHY is powered on
+	 * next time.
+	 */
+	if (qmp->nocsr_reset)
+		goto skip_phy_deinit;
+
 	/* PHY reset */
 	qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
 
@@ -4107,6 +4155,7 @@ static int qmp_pcie_power_off(struct phy *phy)
 	qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
 			cfg->pwrdn_ctrl);
 
+skip_phy_deinit:
 	return 0;
 }
 
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Re: [PATCH v5 2/2] phy: qcom: qmp-pcie: Add PHY register retention support

[Manivannan Sadhasivam]

On Wed, Feb 26, 2025 at 06:36:00PM +0800, Wenbin Yao wrote:
> From: Qiang Yu <quic_qianyu@quicinc.com>
> 
> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the
> whole PHY (hardware and register), no_csr reset only resets PHY hardware
> but retains register values, which means PHY setting can be skipped during
> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled
> after that.
> 
> Hence, determine whether the PHY has been enabled in bootloader by
> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is
> available, skip BCR reset and PHY register setting to establish the PCIe
> link with bootloader - programmed PHY settings.
> 
> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

One nit below.

> ---
>  drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 69 ++++++++++++++++++++----
>  1 file changed, 59 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> index 219266125cf2..c3642d1807e4 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
> @@ -2805,6 +2805,7 @@ struct qmp_pcie {
>  
>  	const struct qmp_phy_cfg *cfg;
>  	bool tcsr_4ln_config;
> +	bool skip_init;
>  
>  	void __iomem *serdes;
>  	void __iomem *pcs;
> @@ -3976,18 +3977,38 @@ static int qmp_pcie_init(struct phy *phy)
>  {
>  	struct qmp_pcie *qmp = phy_get_drvdata(phy);
>  	const struct qmp_phy_cfg *cfg = qmp->cfg;
> +	void __iomem *pcs = qmp->pcs;
> +	bool phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL]));
>  	int ret;
>  
> +	qmp->skip_init = qmp->nocsr_reset && phy_initialized;
> +	/*
> +	 * We need to check the existence of init sequences in two cases:
> +	 * 1. The PHY doesn't support no_csr reset.
> +	 * 2. The PHY supports no_csr reset but isn't initialized by bootloader.
> +	 * As we can't skip init in these two cases.
> +	 */
> +	if (!qmp->skip_init && !cfg->tbls.serdes_num) {
> +		dev_err(qmp->dev, "no init sequences are available\n");

"Init sequence not available\n"

> +		return -EINVAL;

-ENODATA

- Mani

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Re: [PATCH v5 2/2] phy: qcom: qmp-pcie: Add PHY register retention support

[Wenbin Yao (Consultant)]

On 3/14/2025 10:50 PM, Manivannan Sadhasivam wrote:
> On Wed, Feb 26, 2025 at 06:36:00PM +0800, Wenbin Yao wrote:
>> From: Qiang Yu <quic_qianyu@quicinc.com>
>>
>> Some QCOM PCIe PHYs support no_csr reset. Unlike BCR reset which resets the
>> whole PHY (hardware and register), no_csr reset only resets PHY hardware
>> but retains register values, which means PHY setting can be skipped during
>> PHY init if PCIe link is enabled in booltloader and only no_csr is toggled
>> after that.
>>
>> Hence, determine whether the PHY has been enabled in bootloader by
>> verifying QPHY_START_CTRL register. If it's programmed and no_csr reset is
>> available, skip BCR reset and PHY register setting to establish the PCIe
>> link with bootloader - programmed PHY settings.
>>
>> Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
>> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> One nit below.
>
>> ---
>>   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 69 ++++++++++++++++++++----
>>   1 file changed, 59 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> index 219266125cf2..c3642d1807e4 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> @@ -2805,6 +2805,7 @@ struct qmp_pcie {
>>   
>>   	const struct qmp_phy_cfg *cfg;
>>   	bool tcsr_4ln_config;
>> +	bool skip_init;
>>   
>>   	void __iomem *serdes;
>>   	void __iomem *pcs;
>> @@ -3976,18 +3977,38 @@ static int qmp_pcie_init(struct phy *phy)
>>   {
>>   	struct qmp_pcie *qmp = phy_get_drvdata(phy);
>>   	const struct qmp_phy_cfg *cfg = qmp->cfg;
>> +	void __iomem *pcs = qmp->pcs;
>> +	bool phy_initialized = !!(readl(pcs + cfg->regs[QPHY_START_CTRL]));
>>   	int ret;
>>   
>> +	qmp->skip_init = qmp->nocsr_reset && phy_initialized;
>> +	/*
>> +	 * We need to check the existence of init sequences in two cases:
>> +	 * 1. The PHY doesn't support no_csr reset.
>> +	 * 2. The PHY supports no_csr reset but isn't initialized by bootloader.
>> +	 * As we can't skip init in these two cases.
>> +	 */
>> +	if (!qmp->skip_init && !cfg->tbls.serdes_num) {
>> +		dev_err(qmp->dev, "no init sequences are available\n");
> "Init sequence not available\n"
>
>> +		return -EINVAL;
> -ENODATA

Will fix in the next version.

>
> - Mani
>
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Re: [PATCH v5 0/2] phy: qcom: qmp-pcie: Add PCIe PHY no_csr reset support

[Wenbin Yao (Consultant)]

On 2/26/2025 6:35 PM, Wenbin Yao wrote:
> The series aims to skip phy register programming and drive PCIe PHY with
> register setting programmed in bootloader by simply toggling no_csr reset,
> which once togglled, PHY hardware will be reset while PHY registers are
> retained.
>
> First, determine whether PHY setting can be skipped by checking
> QPHY_START_CTRL register and the existence of nocsr reset. If it is
> programmed and no_csr reset is supported, do no_csr reset and skip BCR
> reset which will reset entire PHY.
>
> This series also remove has_nocsr_reset flag in qmp_phy_cfg structure and
> decide whether the PHY supports nocsr reset by checking the existence of
> nocsr reset in device tree.
>
> The series are tested on X1E80100-QCP and HDK8550.
>
> The commit messages of this patchset have been modified based on comments
> and suggestions.
>
> Changes in v5:
> - Add a check whether the init sequences are exist if the PHY needs to be
>    initialized to Patch 2/2.
> - Link to v4: https://lore.kernel.org/all/20250220102253.755116-1-quic_wenbyao@quicinc.com/
>
> Changes in v4:
> - Add Philipp's Reviewed-by tag to Patch 1/2.
> - Use PHY instead of phy in comments in Patch 2/2.
> - Use "if (qmp->nocsr_reset)" instead of "if (!qmp->nocsr_reset)" in
>    function qmp_pcie_exit for readability in Patch 2/2.
> - Use goto statements in function qmp_pcie_power_on and qmp_pcie_power_off
>    for readability in Patch 2/2.
> - Refine the comment of why not checking qmp->skip_init when reset PHY in
>    function qmp_pcie_power_off in Patch 2/2.
> - Link to v3: https://lore.kernel.org/all/20250214104539.281846-1-quic_wenbyao@quicinc.com/
>
> Changes in v3:
> - Replace devm_reset_control_get_exclusive with
>    devm_reset_control_get_optional_exclusive when get phy_nocsr reset
>    control in Patch 1/2.
> - Do not ignore -EINVAL when get phy_nocsr reset control in Patch 1/2.
> - Replace phy_initialized with skip_init in struct qmp_pcie in Patch 2/2.
> - Add a comment to why not check qmp->skip_init in function
>    qmp_pcie_power_off in Patch 2/2.
> - Link to v2: https://lore.kernel.org/all/20250211094231.1813558-1-quic_wenbyao@quicinc.com/
>
> Changes in v2:
> - Add Abel's and Manivannan's Reviewed-by tag to Patch 1/2.
> - Refine commit msg of Patch 2/2.
> - Link to v1: https://lore.kernel.org/all/20250121094140.4006801-1-quic_wenbyao@quicinc.com/
>
> Konrad Dybcio (1):
>    phy: qcom: pcie: Determine has_nocsr_reset dynamically
>
> Qiang Yu (1):
>    phy: qcom: qmp-pcie: Add PHY register retention support
>
>   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 86 +++++++++++++++++-------
>   1 file changed, 63 insertions(+), 23 deletions(-)
>
>
> base-commit: bcf2acd8f64b0a5783deeeb5fd70c6163ec5acd7

Hi, do you have any futher comments?

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Re: [PATCH v5 0/2] phy: qcom: qmp-pcie: Add PCIe PHY no_csr reset support

[Vinod Koul]

On 10-03-25, 16:58, Wenbin Yao (Consultant) wrote:
> On 2/26/2025 6:35 PM, Wenbin Yao wrote:
> > The series aims to skip phy register programming and drive PCIe PHY with
> > register setting programmed in bootloader by simply toggling no_csr reset,
> > which once togglled, PHY hardware will be reset while PHY registers are
> > retained.
> > 
> > First, determine whether PHY setting can be skipped by checking
> > QPHY_START_CTRL register and the existence of nocsr reset. If it is
> > programmed and no_csr reset is supported, do no_csr reset and skip BCR
> > reset which will reset entire PHY.
> > 
> > This series also remove has_nocsr_reset flag in qmp_phy_cfg structure and
> > decide whether the PHY supports nocsr reset by checking the existence of
> > nocsr reset in device tree.
> > 
> > The series are tested on X1E80100-QCP and HDK8550.
> > 
> > The commit messages of this patchset have been modified based on comments
> > and suggestions.
> > 
> > Changes in v5:
> > - Add a check whether the init sequences are exist if the PHY needs to be
> >    initialized to Patch 2/2.
> > - Link to v4: https://lore.kernel.org/all/20250220102253.755116-1-quic_wenbyao@quicinc.com/
> > 
> > Changes in v4:
> > - Add Philipp's Reviewed-by tag to Patch 1/2.
> > - Use PHY instead of phy in comments in Patch 2/2.
> > - Use "if (qmp->nocsr_reset)" instead of "if (!qmp->nocsr_reset)" in
> >    function qmp_pcie_exit for readability in Patch 2/2.
> > - Use goto statements in function qmp_pcie_power_on and qmp_pcie_power_off
> >    for readability in Patch 2/2.
> > - Refine the comment of why not checking qmp->skip_init when reset PHY in
> >    function qmp_pcie_power_off in Patch 2/2.
> > - Link to v3: https://lore.kernel.org/all/20250214104539.281846-1-quic_wenbyao@quicinc.com/
> > 
> > Changes in v3:
> > - Replace devm_reset_control_get_exclusive with
> >    devm_reset_control_get_optional_exclusive when get phy_nocsr reset
> >    control in Patch 1/2.
> > - Do not ignore -EINVAL when get phy_nocsr reset control in Patch 1/2.
> > - Replace phy_initialized with skip_init in struct qmp_pcie in Patch 2/2.
> > - Add a comment to why not check qmp->skip_init in function
> >    qmp_pcie_power_off in Patch 2/2.
> > - Link to v2: https://lore.kernel.org/all/20250211094231.1813558-1-quic_wenbyao@quicinc.com/
> > 
> > Changes in v2:
> > - Add Abel's and Manivannan's Reviewed-by tag to Patch 1/2.
> > - Refine commit msg of Patch 2/2.
> > - Link to v1: https://lore.kernel.org/all/20250121094140.4006801-1-quic_wenbyao@quicinc.com/
> > 
> > Konrad Dybcio (1):
> >    phy: qcom: pcie: Determine has_nocsr_reset dynamically
> > 
> > Qiang Yu (1):
> >    phy: qcom: qmp-pcie: Add PHY register retention support
> > 
> >   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 86 +++++++++++++++++-------
> >   1 file changed, 63 insertions(+), 23 deletions(-)
> > 
> > 
> > base-commit: bcf2acd8f64b0a5783deeeb5fd70c6163ec5acd7
> 
> Hi, do you have any futher comments?

Patches lgtm, It would be great if this was tested by someone as well...
Abel, Stephan, Neil can you folks test this and provide T-B

I am also concerned about bootloader assumptions esp if the Qcom boot
chain is skipped

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Re: [PATCH v5 0/2] phy: qcom: qmp-pcie: Add PCIe PHY no_csr reset support

[Manivannan Sadhasivam]

On Tue, Mar 11, 2025 at 01:29:15AM +0530, Vinod Koul wrote:
> On 10-03-25, 16:58, Wenbin Yao (Consultant) wrote:
> > On 2/26/2025 6:35 PM, Wenbin Yao wrote:
> > > The series aims to skip phy register programming and drive PCIe PHY with
> > > register setting programmed in bootloader by simply toggling no_csr reset,
> > > which once togglled, PHY hardware will be reset while PHY registers are
> > > retained.
> > > 
> > > First, determine whether PHY setting can be skipped by checking
> > > QPHY_START_CTRL register and the existence of nocsr reset. If it is
> > > programmed and no_csr reset is supported, do no_csr reset and skip BCR
> > > reset which will reset entire PHY.
> > > 
> > > This series also remove has_nocsr_reset flag in qmp_phy_cfg structure and
> > > decide whether the PHY supports nocsr reset by checking the existence of
> > > nocsr reset in device tree.
> > > 
> > > The series are tested on X1E80100-QCP and HDK8550.
> > > 
> > > The commit messages of this patchset have been modified based on comments
> > > and suggestions.
> > > 
> > > Changes in v5:
> > > - Add a check whether the init sequences are exist if the PHY needs to be
> > >    initialized to Patch 2/2.
> > > - Link to v4: https://lore.kernel.org/all/20250220102253.755116-1-quic_wenbyao@quicinc.com/
> > > 
> > > Changes in v4:
> > > - Add Philipp's Reviewed-by tag to Patch 1/2.
> > > - Use PHY instead of phy in comments in Patch 2/2.
> > > - Use "if (qmp->nocsr_reset)" instead of "if (!qmp->nocsr_reset)" in
> > >    function qmp_pcie_exit for readability in Patch 2/2.
> > > - Use goto statements in function qmp_pcie_power_on and qmp_pcie_power_off
> > >    for readability in Patch 2/2.
> > > - Refine the comment of why not checking qmp->skip_init when reset PHY in
> > >    function qmp_pcie_power_off in Patch 2/2.
> > > - Link to v3: https://lore.kernel.org/all/20250214104539.281846-1-quic_wenbyao@quicinc.com/
> > > 
> > > Changes in v3:
> > > - Replace devm_reset_control_get_exclusive with
> > >    devm_reset_control_get_optional_exclusive when get phy_nocsr reset
> > >    control in Patch 1/2.
> > > - Do not ignore -EINVAL when get phy_nocsr reset control in Patch 1/2.
> > > - Replace phy_initialized with skip_init in struct qmp_pcie in Patch 2/2.
> > > - Add a comment to why not check qmp->skip_init in function
> > >    qmp_pcie_power_off in Patch 2/2.
> > > - Link to v2: https://lore.kernel.org/all/20250211094231.1813558-1-quic_wenbyao@quicinc.com/
> > > 
> > > Changes in v2:
> > > - Add Abel's and Manivannan's Reviewed-by tag to Patch 1/2.
> > > - Refine commit msg of Patch 2/2.
> > > - Link to v1: https://lore.kernel.org/all/20250121094140.4006801-1-quic_wenbyao@quicinc.com/
> > > 
> > > Konrad Dybcio (1):
> > >    phy: qcom: pcie: Determine has_nocsr_reset dynamically
> > > 
> > > Qiang Yu (1):
> > >    phy: qcom: qmp-pcie: Add PHY register retention support
> > > 
> > >   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 86 +++++++++++++++++-------
> > >   1 file changed, 63 insertions(+), 23 deletions(-)
> > > 
> > > 
> > > base-commit: bcf2acd8f64b0a5783deeeb5fd70c6163ec5acd7
> > 
> > Hi, do you have any futher comments?
> 
> Patches lgtm, It would be great if this was tested by someone as well...
> Abel, Stephan, Neil can you folks test this and provide T-B
> 

I tested the previous version and it worked well on X1P40100-CRD. Will give this
version a go and give my tag.

> I am also concerned about bootloader assumptions esp if the Qcom boot
> chain is skipped
> 

In that case, someone should add the PHY init sequence to the driver. That's why
I wanted to have the check in place to avoid silently failing PHY
initialization. Right now, the driver will error out if there is no init
sequence available.

- Mani

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Re: [PATCH v5 0/2] phy: qcom: qmp-pcie: Add PCIe PHY no_csr reset support

[Konrad Dybcio]

On 3/14/25 3:54 PM, Manivannan Sadhasivam wrote:
> On Tue, Mar 11, 2025 at 01:29:15AM +0530, Vinod Koul wrote:
>> On 10-03-25, 16:58, Wenbin Yao (Consultant) wrote:
>>> On 2/26/2025 6:35 PM, Wenbin Yao wrote:
>>>> The series aims to skip phy register programming and drive PCIe PHY with
>>>> register setting programmed in bootloader by simply toggling no_csr reset,
>>>> which once togglled, PHY hardware will be reset while PHY registers are
>>>> retained.
>>>>
>>>> First, determine whether PHY setting can be skipped by checking
>>>> QPHY_START_CTRL register and the existence of nocsr reset. If it is
>>>> programmed and no_csr reset is supported, do no_csr reset and skip BCR
>>>> reset which will reset entire PHY.
>>>>
>>>> This series also remove has_nocsr_reset flag in qmp_phy_cfg structure and
>>>> decide whether the PHY supports nocsr reset by checking the existence of
>>>> nocsr reset in device tree.
>>>>
>>>> The series are tested on X1E80100-QCP and HDK8550.
>>>>
>>>> The commit messages of this patchset have been modified based on comments
>>>> and suggestions.
>>>>
>>>> Changes in v5:
>>>> - Add a check whether the init sequences are exist if the PHY needs to be
>>>>    initialized to Patch 2/2.
>>>> - Link to v4: https://lore.kernel.org/all/20250220102253.755116-1-quic_wenbyao@quicinc.com/
>>>>
>>>> Changes in v4:
>>>> - Add Philipp's Reviewed-by tag to Patch 1/2.
>>>> - Use PHY instead of phy in comments in Patch 2/2.
>>>> - Use "if (qmp->nocsr_reset)" instead of "if (!qmp->nocsr_reset)" in
>>>>    function qmp_pcie_exit for readability in Patch 2/2.
>>>> - Use goto statements in function qmp_pcie_power_on and qmp_pcie_power_off
>>>>    for readability in Patch 2/2.
>>>> - Refine the comment of why not checking qmp->skip_init when reset PHY in
>>>>    function qmp_pcie_power_off in Patch 2/2.
>>>> - Link to v3: https://lore.kernel.org/all/20250214104539.281846-1-quic_wenbyao@quicinc.com/
>>>>
>>>> Changes in v3:
>>>> - Replace devm_reset_control_get_exclusive with
>>>>    devm_reset_control_get_optional_exclusive when get phy_nocsr reset
>>>>    control in Patch 1/2.
>>>> - Do not ignore -EINVAL when get phy_nocsr reset control in Patch 1/2.
>>>> - Replace phy_initialized with skip_init in struct qmp_pcie in Patch 2/2.
>>>> - Add a comment to why not check qmp->skip_init in function
>>>>    qmp_pcie_power_off in Patch 2/2.
>>>> - Link to v2: https://lore.kernel.org/all/20250211094231.1813558-1-quic_wenbyao@quicinc.com/
>>>>
>>>> Changes in v2:
>>>> - Add Abel's and Manivannan's Reviewed-by tag to Patch 1/2.
>>>> - Refine commit msg of Patch 2/2.
>>>> - Link to v1: https://lore.kernel.org/all/20250121094140.4006801-1-quic_wenbyao@quicinc.com/
>>>>
>>>> Konrad Dybcio (1):
>>>>    phy: qcom: pcie: Determine has_nocsr_reset dynamically
>>>>
>>>> Qiang Yu (1):
>>>>    phy: qcom: qmp-pcie: Add PHY register retention support
>>>>
>>>>   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 86 +++++++++++++++++-------
>>>>   1 file changed, 63 insertions(+), 23 deletions(-)
>>>>
>>>>
>>>> base-commit: bcf2acd8f64b0a5783deeeb5fd70c6163ec5acd7
>>>
>>> Hi, do you have any futher comments?
>>
>> Patches lgtm, It would be great if this was tested by someone as well...
>> Abel, Stephan, Neil can you folks test this and provide T-B
>>
> 
> I tested the previous version and it worked well on X1P40100-CRD. Will give this
> version a go and give my tag.
> 
>> I am also concerned about bootloader assumptions esp if the Qcom boot
>> chain is skipped

If any major part of this boot chain is skipped, much of the platform will
unfortunately not behave as expected by the kernel today, anyway. While I
personally enjoy hacking on such things, holding back hw support because of
theoretical issues is not going to help here, especially since the tables
can be trivially added at a later point, if ever needed, without requiring
DT changes.

> In that case, someone should add the PHY init sequence to the driver. That's why
> I wanted to have the check in place to avoid silently failing PHY
> initialization. Right now, the driver will error out if there is no init
> sequence available.

IIUC we internally settled on not sending the sequences for X1P4, since
the PHYs are initialized as expected.

Konrad

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